Lines Matching +full:domain +full:- +full:idle +full:- +full:state
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,icc.h>
10 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom,rpmhpd.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board: xo-board {
26 compatible = "fixed-clock";
27 clock-frequency = <76800000>;
28 #clock-cells = <0>;
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
33 clock-frequency = <32000>;
34 #clock-cells = <0>;
37 bi_tcxo_div2: bi-tcxo-div2-clk {
38 compatible = "fixed-factor-clock";
39 #clock-cells = <0>;
42 clock-mult = <1>;
43 clock-div = <2>;
46 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
47 compatible = "fixed-factor-clock";
48 #clock-cells = <0>;
51 clock-mult = <1>;
52 clock-div = <2>;
57 #address-cells = <2>;
58 #size-cells = <0>;
64 enable-method = "psci";
65 next-level-cache = <&L2_0>;
66 power-domains = <&CPU_PD0>;
67 power-domain-names = "psci";
68 cpu-idle-states = <&CLUSTER_C4>;
70 L2_0: l2-cache {
72 cache-level = <2>;
73 cache-unified;
81 enable-method = "psci";
82 next-level-cache = <&L2_0>;
83 power-domains = <&CPU_PD1>;
84 power-domain-names = "psci";
85 cpu-idle-states = <&CLUSTER_C4>;
92 enable-method = "psci";
93 next-level-cache = <&L2_0>;
94 power-domains = <&CPU_PD2>;
95 power-domain-names = "psci";
96 cpu-idle-states = <&CLUSTER_C4>;
103 enable-method = "psci";
104 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_PD3>;
106 power-domain-names = "psci";
107 cpu-idle-states = <&CLUSTER_C4>;
114 enable-method = "psci";
115 next-level-cache = <&L2_1>;
116 power-domains = <&CPU_PD4>;
117 power-domain-names = "psci";
118 cpu-idle-states = <&CLUSTER_C4>;
120 L2_1: l2-cache {
122 cache-level = <2>;
123 cache-unified;
131 enable-method = "psci";
132 next-level-cache = <&L2_1>;
133 power-domains = <&CPU_PD5>;
134 power-domain-names = "psci";
135 cpu-idle-states = <&CLUSTER_C4>;
142 enable-method = "psci";
143 next-level-cache = <&L2_1>;
144 power-domains = <&CPU_PD6>;
145 power-domain-names = "psci";
146 cpu-idle-states = <&CLUSTER_C4>;
153 enable-method = "psci";
154 next-level-cache = <&L2_1>;
155 power-domains = <&CPU_PD7>;
156 power-domain-names = "psci";
157 cpu-idle-states = <&CLUSTER_C4>;
164 enable-method = "psci";
165 next-level-cache = <&L2_2>;
166 power-domains = <&CPU_PD8>;
167 power-domain-names = "psci";
168 cpu-idle-states = <&CLUSTER_C4>;
170 L2_2: l2-cache {
172 cache-level = <2>;
173 cache-unified;
181 enable-method = "psci";
182 next-level-cache = <&L2_2>;
183 power-domains = <&CPU_PD9>;
184 power-domain-names = "psci";
185 cpu-idle-states = <&CLUSTER_C4>;
192 enable-method = "psci";
193 next-level-cache = <&L2_2>;
194 power-domains = <&CPU_PD10>;
195 power-domain-names = "psci";
196 cpu-idle-states = <&CLUSTER_C4>;
203 enable-method = "psci";
204 next-level-cache = <&L2_2>;
205 power-domains = <&CPU_PD11>;
206 power-domain-names = "psci";
207 cpu-idle-states = <&CLUSTER_C4>;
210 cpu-map {
266 idle-states {
267 entry-method = "psci";
269 CLUSTER_C4: cpu-sleep-0 {
270 compatible = "arm,idle-state";
271 idle-state-name = "ret";
272 arm,psci-suspend-param = <0x00000004>;
273 entry-latency-us = <180>;
274 exit-latency-us = <320>;
275 min-residency-us = <1000>;
279 domain-idle-states {
280 CLUSTER_CL4: cluster-sleep-0 {
281 compatible = "arm,idle-state";
282 idle-state-name = "l2-ret";
283 arm,psci-suspend-param = <0x01000044>;
284 entry-latency-us = <350>;
285 exit-latency-us = <500>;
286 min-residency-us = <2500>;
289 CLUSTER_CL5: cluster-sleep-1 {
290 compatible = "arm,idle-state";
291 idle-state-name = "ret-pll-off";
292 arm,psci-suspend-param = <0x01000054>;
293 entry-latency-us = <2200>;
294 exit-latency-us = <2500>;
295 min-residency-us = <7000>;
302 compatible = "qcom,scm-x1e80100", "qcom,scm";
308 clk_virt: interconnect-0 {
309 compatible = "qcom,x1e80100-clk-virt";
310 #interconnect-cells = <2>;
311 qcom,bcm-voters = <&apps_bcm_voter>;
314 mc_virt: interconnect-1 {
315 compatible = "qcom,x1e80100-mc-virt";
316 #interconnect-cells = <2>;
317 qcom,bcm-voters = <&apps_bcm_voter>;
327 compatible = "arm,armv8-pmuv3";
332 compatible = "arm,psci-1.0";
335 CPU_PD0: power-domain-cpu0 {
336 #power-domain-cells = <0>;
337 power-domains = <&CLUSTER_PD0>;
340 CPU_PD1: power-domain-cpu1 {
341 #power-domain-cells = <0>;
342 power-domains = <&CLUSTER_PD0>;
345 CPU_PD2: power-domain-cpu2 {
346 #power-domain-cells = <0>;
347 power-domains = <&CLUSTER_PD0>;
350 CPU_PD3: power-domain-cpu3 {
351 #power-domain-cells = <0>;
352 power-domains = <&CLUSTER_PD0>;
355 CPU_PD4: power-domain-cpu4 {
356 #power-domain-cells = <0>;
357 power-domains = <&CLUSTER_PD1>;
360 CPU_PD5: power-domain-cpu5 {
361 #power-domain-cells = <0>;
362 power-domains = <&CLUSTER_PD1>;
365 CPU_PD6: power-domain-cpu6 {
366 #power-domain-cells = <0>;
367 power-domains = <&CLUSTER_PD1>;
370 CPU_PD7: power-domain-cpu7 {
371 #power-domain-cells = <0>;
372 power-domains = <&CLUSTER_PD1>;
375 CPU_PD8: power-domain-cpu8 {
376 #power-domain-cells = <0>;
377 power-domains = <&CLUSTER_PD2>;
380 CPU_PD9: power-domain-cpu9 {
381 #power-domain-cells = <0>;
382 power-domains = <&CLUSTER_PD2>;
385 CPU_PD10: power-domain-cpu10 {
386 #power-domain-cells = <0>;
387 power-domains = <&CLUSTER_PD2>;
390 CPU_PD11: power-domain-cpu11 {
391 #power-domain-cells = <0>;
392 power-domains = <&CLUSTER_PD2>;
395 CLUSTER_PD0: power-domain-cpu-cluster0 {
396 #power-domain-cells = <0>;
397 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
400 CLUSTER_PD1: power-domain-cpu-cluster1 {
401 #power-domain-cells = <0>;
402 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
405 CLUSTER_PD2: power-domain-cpu-cluster2 {
406 #power-domain-cells = <0>;
407 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
411 reserved-memory {
412 #address-cells = <2>;
413 #size-cells = <2>;
416 gunyah_hyp_mem: gunyah-hyp@80000000 {
418 no-map;
421 hyp_elf_package_mem: hyp-elf-package@80800000 {
423 no-map;
428 no-map;
431 cpucp_log_mem: cpucp-log@80e00000 {
433 no-map;
438 no-map;
441 reserved-region@81380000 {
443 no-map;
446 tags_mem: tags-region@81400000 {
448 no-map;
451 xbl_dtlog_mem: xbl-dtlog@81a00000 {
453 no-map;
456 xbl_ramdump_mem: xbl-ramdump@81a40000 {
458 no-map;
461 aop_image_mem: aop-image@81c00000 {
463 no-map;
466 aop_cmd_db_mem: aop-cmd-db@81c60000 {
467 compatible = "qcom,cmd-db";
469 no-map;
472 aop_config_mem: aop-config@81c80000 {
474 no-map;
477 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
479 no-map;
482 tme_log_mem: tme-log@81ce0000 {
484 no-map;
487 uefi_log_mem: uefi-log@81ce4000 {
489 no-map;
492 secdata_apss_mem: secdata-apss@81cff000 {
494 no-map;
497 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
499 no-map;
502 gpu_prr_mem: gpu-prr@81f00000 {
504 no-map;
507 tpm_control_mem: tpm-control@81f10000 {
509 no-map;
512 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
514 no-map;
517 pld_pep_mem: pld-pep@81f30000 {
519 no-map;
522 pld_gmu_mem: pld-gmu@81f36000 {
524 no-map;
527 pld_pdp_mem: pld-pdp@81f37000 {
529 no-map;
532 tz_stat_mem: tz-stat@82700000 {
534 no-map;
537 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
539 no-map;
542 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
544 no-map;
547 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
549 no-map;
552 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
554 no-map;
557 spss_region_mem: spss-region@86700000 {
559 no-map;
562 adsp_boot_mem: adsp-boot@86b00000 {
564 no-map;
569 no-map;
574 no-map;
577 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
579 no-map;
584 no-map;
587 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
589 no-map;
592 gpu_microcode_mem: gpu-microcode@8d9fe000 {
594 no-map;
599 no-map;
604 no-map;
607 av1_encoder_mem: av1-encoder@8e900000 {
609 no-map;
612 reserved-region@8f000000 {
614 no-map;
619 no-map;
622 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
624 no-map;
627 xbl_sc_mem: xbl-sc@d8000000 {
629 no-map;
632 reserved-region@d8040000 {
634 no-map;
639 no-map;
644 no-map;
649 no-map;
652 llcc_lpi_mem: llcc-lpi@ff800000 {
654 no-map;
661 no-map;
666 compatible = "simple-bus";
668 #address-cells = <2>;
669 #size-cells = <2>;
670 dma-ranges = <0 0 0 0 0x10 0>;
673 gcc: clock-controller@100000 {
674 compatible = "qcom,x1e80100-gcc";
688 power-domains = <&rpmhpd RPMHPD_CX>;
689 #clock-cells = <1>;
690 #reset-cells = <1>;
691 #power-domain-cells = <1>;
694 gpi_dma2: dma-controller@800000 {
695 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
711 dma-channels = <12>;
712 dma-channel-mask = <0x3e>;
713 #dma-cells = <3>;
721 compatible = "qcom,geni-se-qup";
726 clock-names = "m-ahb",
727 "s-ahb";
731 #address-cells = <2>;
732 #size-cells = <2>;
738 compatible = "qcom,geni-i2c";
744 clock-names = "se";
752 interconnect-names = "qup-core",
753 "qup-config",
754 "qup-memory";
758 dma-names = "tx",
761 pinctrl-0 = <&qup_i2c16_data_clk>;
762 pinctrl-names = "default";
764 #address-cells = <1>;
765 #size-cells = <0>;
771 compatible = "qcom,geni-spi";
777 clock-names = "se";
785 interconnect-names = "qup-core",
786 "qup-config",
787 "qup-memory";
791 dma-names = "tx",
794 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
795 pinctrl-names = "default";
797 #address-cells = <1>;
798 #size-cells = <0>;
804 compatible = "qcom,geni-i2c";
810 clock-names = "se";
818 interconnect-names = "qup-core",
819 "qup-config",
820 "qup-memory";
824 dma-names = "tx",
827 pinctrl-0 = <&qup_i2c17_data_clk>;
828 pinctrl-names = "default";
830 #address-cells = <1>;
831 #size-cells = <0>;
837 compatible = "qcom,geni-spi";
843 clock-names = "se";
851 interconnect-names = "qup-core",
852 "qup-config",
853 "qup-memory";
857 dma-names = "tx",
860 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
861 pinctrl-names = "default";
863 #address-cells = <1>;
864 #size-cells = <0>;
870 compatible = "qcom,geni-i2c";
876 clock-names = "se";
884 interconnect-names = "qup-core",
885 "qup-config",
886 "qup-memory";
890 dma-names = "tx",
893 pinctrl-0 = <&qup_i2c18_data_clk>;
894 pinctrl-names = "default";
896 #address-cells = <1>;
897 #size-cells = <0>;
903 compatible = "qcom,geni-spi";
909 clock-names = "se";
917 interconnect-names = "qup-core",
918 "qup-config",
919 "qup-memory";
923 dma-names = "tx",
926 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
927 pinctrl-names = "default";
929 #address-cells = <1>;
930 #size-cells = <0>;
936 compatible = "qcom,geni-i2c";
942 clock-names = "se";
950 interconnect-names = "qup-core",
951 "qup-config",
952 "qup-memory";
956 dma-names = "tx",
959 pinctrl-0 = <&qup_i2c19_data_clk>;
960 pinctrl-names = "default";
962 #address-cells = <1>;
963 #size-cells = <0>;
969 compatible = "qcom,geni-spi";
975 clock-names = "se";
983 interconnect-names = "qup-core",
984 "qup-config",
985 "qup-memory";
989 dma-names = "tx",
992 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
993 pinctrl-names = "default";
995 #address-cells = <1>;
996 #size-cells = <0>;
1002 compatible = "qcom,geni-i2c";
1008 clock-names = "se";
1016 interconnect-names = "qup-core",
1017 "qup-config",
1018 "qup-memory";
1022 dma-names = "tx",
1025 pinctrl-0 = <&qup_i2c20_data_clk>;
1026 pinctrl-names = "default";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1035 compatible = "qcom,geni-spi";
1041 clock-names = "se";
1049 interconnect-names = "qup-core",
1050 "qup-config",
1051 "qup-memory";
1055 dma-names = "tx",
1058 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1059 pinctrl-names = "default";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1068 compatible = "qcom,geni-i2c";
1074 clock-names = "se";
1082 interconnect-names = "qup-core",
1083 "qup-config",
1084 "qup-memory";
1088 dma-names = "tx",
1091 pinctrl-0 = <&qup_i2c21_data_clk>;
1092 pinctrl-names = "default";
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1101 compatible = "qcom,geni-spi";
1107 clock-names = "se";
1115 interconnect-names = "qup-core",
1116 "qup-config",
1117 "qup-memory";
1121 dma-names = "tx",
1124 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1125 pinctrl-names = "default";
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1134 compatible = "qcom,geni-uart";
1140 clock-names = "se";
1146 interconnect-names = "qup-core",
1147 "qup-config";
1149 pinctrl-0 = <&qup_uart21_default>;
1150 pinctrl-names = "default";
1156 compatible = "qcom,geni-i2c";
1162 clock-names = "se";
1170 interconnect-names = "qup-core",
1171 "qup-config",
1172 "qup-memory";
1176 dma-names = "tx",
1179 pinctrl-0 = <&qup_i2c22_data_clk>;
1180 pinctrl-names = "default";
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1189 compatible = "qcom,geni-spi";
1195 clock-names = "se";
1203 interconnect-names = "qup-core",
1204 "qup-config",
1205 "qup-memory";
1209 dma-names = "tx",
1212 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1213 pinctrl-names = "default";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1222 compatible = "qcom,geni-i2c";
1228 clock-names = "se";
1236 interconnect-names = "qup-core",
1237 "qup-config",
1238 "qup-memory";
1242 dma-names = "tx",
1245 pinctrl-0 = <&qup_i2c23_data_clk>;
1246 pinctrl-names = "default";
1248 #address-cells = <1>;
1249 #size-cells = <0>;
1255 compatible = "qcom,geni-spi";
1261 clock-names = "se";
1269 interconnect-names = "qup-core",
1270 "qup-config",
1271 "qup-memory";
1275 dma-names = "tx",
1278 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1279 pinctrl-names = "default";
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1288 gpi_dma1: dma-controller@a00000 {
1289 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1305 dma-channels = <12>;
1306 dma-channel-mask = <0x3e>;
1307 #dma-cells = <3>;
1315 compatible = "qcom,geni-se-qup";
1320 clock-names = "m-ahb",
1321 "s-ahb";
1325 #address-cells = <2>;
1326 #size-cells = <2>;
1332 compatible = "qcom,geni-i2c";
1338 clock-names = "se";
1346 interconnect-names = "qup-core",
1347 "qup-config",
1348 "qup-memory";
1352 dma-names = "tx",
1355 pinctrl-0 = <&qup_i2c8_data_clk>;
1356 pinctrl-names = "default";
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1365 compatible = "qcom,geni-spi";
1371 clock-names = "se";
1379 interconnect-names = "qup-core",
1380 "qup-config",
1381 "qup-memory";
1385 dma-names = "tx",
1388 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1389 pinctrl-names = "default";
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1398 compatible = "qcom,geni-i2c";
1404 clock-names = "se";
1412 interconnect-names = "qup-core",
1413 "qup-config",
1414 "qup-memory";
1418 dma-names = "tx",
1421 pinctrl-0 = <&qup_i2c9_data_clk>;
1422 pinctrl-names = "default";
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1431 compatible = "qcom,geni-spi";
1437 clock-names = "se";
1445 interconnect-names = "qup-core",
1446 "qup-config",
1447 "qup-memory";
1451 dma-names = "tx",
1454 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1455 pinctrl-names = "default";
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1464 compatible = "qcom,geni-i2c";
1470 clock-names = "se";
1478 interconnect-names = "qup-core",
1479 "qup-config",
1480 "qup-memory";
1484 dma-names = "tx",
1487 pinctrl-0 = <&qup_i2c10_data_clk>;
1488 pinctrl-names = "default";
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1497 compatible = "qcom,geni-spi";
1503 clock-names = "se";
1511 interconnect-names = "qup-core",
1512 "qup-config",
1513 "qup-memory";
1517 dma-names = "tx",
1520 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1521 pinctrl-names = "default";
1523 #address-cells = <1>;
1524 #size-cells = <0>;
1530 compatible = "qcom,geni-i2c";
1536 clock-names = "se";
1544 interconnect-names = "qup-core",
1545 "qup-config",
1546 "qup-memory";
1550 dma-names = "tx",
1553 pinctrl-0 = <&qup_i2c11_data_clk>;
1554 pinctrl-names = "default";
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1563 compatible = "qcom,geni-spi";
1569 clock-names = "se";
1577 interconnect-names = "qup-core",
1578 "qup-config",
1579 "qup-memory";
1583 dma-names = "tx",
1586 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1587 pinctrl-names = "default";
1589 #address-cells = <1>;
1590 #size-cells = <0>;
1596 compatible = "qcom,geni-i2c";
1602 clock-names = "se";
1610 interconnect-names = "qup-core",
1611 "qup-config",
1612 "qup-memory";
1616 dma-names = "tx",
1619 pinctrl-0 = <&qup_i2c12_data_clk>;
1620 pinctrl-names = "default";
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1629 compatible = "qcom,geni-spi";
1635 clock-names = "se";
1643 interconnect-names = "qup-core",
1644 "qup-config",
1645 "qup-memory";
1649 dma-names = "tx",
1652 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1653 pinctrl-names = "default";
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1662 compatible = "qcom,geni-i2c";
1668 clock-names = "se";
1676 interconnect-names = "qup-core",
1677 "qup-config",
1678 "qup-memory";
1682 dma-names = "tx",
1685 pinctrl-0 = <&qup_i2c13_data_clk>;
1686 pinctrl-names = "default";
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1695 compatible = "qcom,geni-spi";
1701 clock-names = "se";
1709 interconnect-names = "qup-core",
1710 "qup-config",
1711 "qup-memory";
1715 dma-names = "tx",
1718 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1719 pinctrl-names = "default";
1721 #address-cells = <1>;
1722 #size-cells = <0>;
1728 compatible = "qcom,geni-i2c";
1734 clock-names = "se";
1742 interconnect-names = "qup-core",
1743 "qup-config",
1744 "qup-memory";
1748 dma-names = "tx",
1751 pinctrl-0 = <&qup_i2c14_data_clk>;
1752 pinctrl-names = "default";
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1761 compatible = "qcom,geni-spi";
1767 clock-names = "se";
1775 interconnect-names = "qup-core",
1776 "qup-config",
1777 "qup-memory";
1781 dma-names = "tx",
1784 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1785 pinctrl-names = "default";
1787 #address-cells = <1>;
1788 #size-cells = <0>;
1794 compatible = "qcom,geni-i2c";
1800 clock-names = "se";
1808 interconnect-names = "qup-core",
1809 "qup-config",
1810 "qup-memory";
1814 dma-names = "tx",
1817 pinctrl-0 = <&qup_i2c15_data_clk>;
1818 pinctrl-names = "default";
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1827 compatible = "qcom,geni-spi";
1833 clock-names = "se";
1841 interconnect-names = "qup-core",
1842 "qup-config",
1843 "qup-memory";
1847 dma-names = "tx",
1850 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1851 pinctrl-names = "default";
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1860 gpi_dma0: dma-controller@b00000 {
1861 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1877 dma-channels = <12>;
1878 dma-channel-mask = <0x3e>;
1879 #dma-cells = <3>;
1887 compatible = "qcom,geni-se-qup";
1892 clock-names = "m-ahb",
1893 "s-ahb";
1896 #address-cells = <2>;
1897 #size-cells = <2>;
1903 compatible = "qcom,geni-i2c";
1909 clock-names = "se";
1917 interconnect-names = "qup-core",
1918 "qup-config",
1919 "qup-memory";
1923 dma-names = "tx",
1926 pinctrl-0 = <&qup_i2c0_data_clk>;
1927 pinctrl-names = "default";
1929 #address-cells = <1>;
1930 #size-cells = <0>;
1936 compatible = "qcom,geni-spi";
1942 clock-names = "se";
1950 interconnect-names = "qup-core",
1951 "qup-config",
1952 "qup-memory";
1956 dma-names = "tx",
1959 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1960 pinctrl-names = "default";
1962 #address-cells = <1>;
1963 #size-cells = <0>;
1969 compatible = "qcom,geni-i2c";
1975 clock-names = "se";
1983 interconnect-names = "qup-core",
1984 "qup-config",
1985 "qup-memory";
1989 dma-names = "tx",
1992 pinctrl-0 = <&qup_i2c1_data_clk>;
1993 pinctrl-names = "default";
1995 #address-cells = <1>;
1996 #size-cells = <0>;
2002 compatible = "qcom,geni-spi";
2008 clock-names = "se";
2016 interconnect-names = "qup-core",
2017 "qup-config",
2018 "qup-memory";
2022 dma-names = "tx",
2025 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2026 pinctrl-names = "default";
2028 #address-cells = <1>;
2029 #size-cells = <0>;
2035 compatible = "qcom,geni-i2c";
2041 clock-names = "se";
2049 interconnect-names = "qup-core",
2050 "qup-config",
2051 "qup-memory";
2055 dma-names = "tx",
2058 pinctrl-0 = <&qup_i2c2_data_clk>;
2059 pinctrl-names = "default";
2061 #address-cells = <1>;
2062 #size-cells = <0>;
2068 compatible = "qcom,geni-spi";
2074 clock-names = "se";
2082 interconnect-names = "qup-core",
2083 "qup-config",
2084 "qup-memory";
2088 dma-names = "tx",
2091 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2092 pinctrl-names = "default";
2094 #address-cells = <1>;
2095 #size-cells = <0>;
2101 compatible = "qcom,geni-i2c";
2107 clock-names = "se";
2115 interconnect-names = "qup-core",
2116 "qup-config",
2117 "qup-memory";
2121 dma-names = "tx",
2124 pinctrl-0 = <&qup_i2c3_data_clk>;
2125 pinctrl-names = "default";
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2134 compatible = "qcom,geni-spi";
2140 clock-names = "se";
2148 interconnect-names = "qup-core",
2149 "qup-config",
2150 "qup-memory";
2154 dma-names = "tx",
2157 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2158 pinctrl-names = "default";
2160 #address-cells = <1>;
2161 #size-cells = <0>;
2167 compatible = "qcom,geni-i2c";
2173 clock-names = "se";
2181 interconnect-names = "qup-core",
2182 "qup-config",
2183 "qup-memory";
2187 dma-names = "tx",
2190 pinctrl-0 = <&qup_i2c4_data_clk>;
2191 pinctrl-names = "default";
2193 #address-cells = <1>;
2194 #size-cells = <0>;
2200 compatible = "qcom,geni-spi";
2206 clock-names = "se";
2214 interconnect-names = "qup-core",
2215 "qup-config",
2216 "qup-memory";
2220 dma-names = "tx",
2223 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2224 pinctrl-names = "default";
2226 #address-cells = <1>;
2227 #size-cells = <0>;
2233 compatible = "qcom,geni-i2c";
2239 clock-names = "se";
2247 interconnect-names = "qup-core",
2248 "qup-config",
2249 "qup-memory";
2253 dma-names = "tx",
2256 pinctrl-0 = <&qup_i2c5_data_clk>;
2257 pinctrl-names = "default";
2259 #address-cells = <1>;
2260 #size-cells = <0>;
2266 compatible = "qcom,geni-spi";
2272 clock-names = "se";
2280 interconnect-names = "qup-core",
2281 "qup-config",
2282 "qup-memory";
2286 dma-names = "tx",
2289 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2290 pinctrl-names = "default";
2292 #address-cells = <1>;
2293 #size-cells = <0>;
2299 compatible = "qcom,geni-i2c";
2305 clock-names = "se";
2313 interconnect-names = "qup-core",
2314 "qup-config",
2315 "qup-memory";
2319 dma-names = "tx",
2322 pinctrl-0 = <&qup_i2c6_data_clk>;
2323 pinctrl-names = "default";
2325 #address-cells = <1>;
2326 #size-cells = <0>;
2332 compatible = "qcom,geni-spi";
2338 clock-names = "se";
2346 interconnect-names = "qup-core",
2347 "qup-config",
2348 "qup-memory";
2352 dma-names = "tx",
2355 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2356 pinctrl-names = "default";
2358 #address-cells = <1>;
2359 #size-cells = <0>;
2365 compatible = "qcom,geni-i2c";
2371 clock-names = "se";
2379 interconnect-names = "qup-core",
2380 "qup-config",
2381 "qup-memory";
2385 dma-names = "tx",
2388 pinctrl-0 = <&qup_i2c7_data_clk>;
2389 pinctrl-names = "default";
2391 #address-cells = <1>;
2392 #size-cells = <0>;
2398 compatible = "qcom,geni-spi";
2404 clock-names = "se";
2412 interconnect-names = "qup-core",
2413 "qup-config",
2414 "qup-memory";
2418 dma-names = "tx",
2421 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2422 pinctrl-names = "default";
2424 #address-cells = <1>;
2425 #size-cells = <0>;
2432 compatible = "qcom,x1e80100-cnoc-main";
2435 qcom,bcm-voters = <&apps_bcm_voter>;
2437 #interconnect-cells = <2>;
2441 compatible = "qcom,x1e80100-cnoc-cfg";
2444 qcom,bcm-voters = <&apps_bcm_voter>;
2446 #interconnect-cells = <2>;
2450 compatible = "qcom,x1e80100-system-noc";
2453 qcom,bcm-voters = <&apps_bcm_voter>;
2455 #interconnect-cells = <2>;
2459 compatible = "qcom,x1e80100-pcie-south-anoc";
2462 qcom,bcm-voters = <&apps_bcm_voter>;
2464 #interconnect-cells = <2>;
2468 compatible = "qcom,x1e80100-pcie-center-anoc";
2471 qcom,bcm-voters = <&apps_bcm_voter>;
2473 #interconnect-cells = <2>;
2477 compatible = "qcom,x1e80100-aggre1-noc";
2480 qcom,bcm-voters = <&apps_bcm_voter>;
2482 #interconnect-cells = <2>;
2486 compatible = "qcom,x1e80100-aggre2-noc";
2489 qcom,bcm-voters = <&apps_bcm_voter>;
2491 #interconnect-cells = <2>;
2495 compatible = "qcom,x1e80100-pcie-north-anoc";
2498 qcom,bcm-voters = <&apps_bcm_voter>;
2500 #interconnect-cells = <2>;
2504 compatible = "qcom,x1e80100-usb-center-anoc";
2507 qcom,bcm-voters = <&apps_bcm_voter>;
2509 #interconnect-cells = <2>;
2513 compatible = "qcom,x1e80100-usb-north-anoc";
2516 qcom,bcm-voters = <&apps_bcm_voter>;
2518 #interconnect-cells = <2>;
2522 compatible = "qcom,x1e80100-usb-south-anoc";
2525 qcom,bcm-voters = <&apps_bcm_voter>;
2527 #interconnect-cells = <2>;
2531 compatible = "qcom,x1e80100-mmss-noc";
2534 qcom,bcm-voters = <&apps_bcm_voter>;
2536 #interconnect-cells = <2>;
2540 compatible = "qcom,tcsr-mutex";
2542 #hwlock-cells = <1>;
2546 compatible = "qcom,x1e80100-gem-noc";
2549 qcom,bcm-voters = <&apps_bcm_voter>;
2551 #interconnect-cells = <2>;
2555 compatible = "qcom,x1e80100-nsp-noc";
2558 qcom,bcm-voters = <&apps_bcm_voter>;
2560 #interconnect-cells = <2>;
2564 compatible = "qcom,x1e80100-lpass-ag-noc";
2567 qcom,bcm-voters = <&apps_bcm_voter>;
2569 #interconnect-cells = <2>;
2573 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
2576 qcom,bcm-voters = <&apps_bcm_voter>;
2578 #interconnect-cells = <2>;
2582 compatible = "qcom,x1e80100-lpass-lpicx-noc";
2585 qcom,bcm-voters = <&apps_bcm_voter>;
2587 #interconnect-cells = <2>;
2590 pdc: interrupt-controller@b220000 {
2591 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
2594 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
2597 #interrupt-cells = <2>;
2598 interrupt-parent = <&intc>;
2599 interrupt-controller;
2603 compatible = "qcom,x1e80100-tlmm";
2608 gpio-controller;
2609 #gpio-cells = <2>;
2611 interrupt-controller;
2612 #interrupt-cells = <2>;
2614 gpio-ranges = <&tlmm 0 0 239>;
2615 wakeup-parent = <&pdc>;
2617 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2621 drive-strength = <2>;
2622 bias-pull-up = <2200>;
2625 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2629 drive-strength = <2>;
2630 bias-pull-up = <2200>;
2633 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2637 drive-strength = <2>;
2638 bias-pull-up = <2200>;
2641 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2645 drive-strength = <2>;
2646 bias-pull-up = <2200>;
2649 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2653 drive-strength = <2>;
2654 bias-pull-up = <2200>;
2657 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2661 drive-strength = <2>;
2662 bias-pull-up = <2200>;
2665 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2669 drive-strength = <2>;
2670 bias-pull-up = <2200>;
2673 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
2677 drive-strength = <2>;
2678 bias-pull-up = <2200>;
2681 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2685 drive-strength = <2>;
2686 bias-pull-up = <2200>;
2689 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2693 drive-strength = <2>;
2694 bias-pull-up = <2200>;
2697 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2701 drive-strength = <2>;
2702 bias-pull-up = <2200>;
2705 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
2709 drive-strength = <2>;
2710 bias-pull-up = <2200>;
2713 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
2717 drive-strength = <2>;
2718 bias-pull-up = <2200>;
2721 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
2725 drive-strength = <2>;
2726 bias-pull-up = <2200>;
2729 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
2733 drive-strength = <2>;
2734 bias-pull-up = <2200>;
2737 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
2741 drive-strength = <2>;
2742 bias-pull-up = <2200>;
2745 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
2749 drive-strength = <2>;
2750 bias-pull-up = <2200>;
2753 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
2757 drive-strength = <2>;
2758 bias-pull-up = <2200>;
2761 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
2765 drive-strength = <2>;
2766 bias-pull-up = <2200>;
2769 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
2773 drive-strength = <2>;
2774 bias-pull-up = <2200>;
2777 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
2781 drive-strength = <2>;
2782 bias-pull-up = <2200>;
2785 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
2789 drive-strength = <2>;
2790 bias-pull-up = <2200>;
2793 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
2797 drive-strength = <2>;
2798 bias-pull-up = <2200>;
2801 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
2805 drive-strength = <2>;
2806 bias-pull-up = <2200>;
2809 qup_spi0_cs: qup-spi0-cs-state {
2812 drive-strength = <6>;
2813 bias-disable;
2816 qup_spi0_data_clk: qup-spi0-data-clk-state {
2820 drive-strength = <6>;
2821 bias-disable;
2824 qup_spi1_cs: qup-spi1-cs-state {
2827 drive-strength = <6>;
2828 bias-disable;
2831 qup_spi1_data_clk: qup-spi1-data-clk-state {
2835 drive-strength = <6>;
2836 bias-disable;
2839 qup_spi2_cs: qup-spi2-cs-state {
2842 drive-strength = <6>;
2843 bias-disable;
2846 qup_spi2_data_clk: qup-spi2-data-clk-state {
2850 drive-strength = <6>;
2851 bias-disable;
2854 qup_spi3_cs: qup-spi3-cs-state {
2857 drive-strength = <6>;
2858 bias-disable;
2861 qup_spi3_data_clk: qup-spi3-data-clk-state {
2865 drive-strength = <6>;
2866 bias-disable;
2869 qup_spi4_cs: qup-spi4-cs-state {
2872 drive-strength = <6>;
2873 bias-disable;
2876 qup_spi4_data_clk: qup-spi4-data-clk-state {
2880 drive-strength = <6>;
2881 bias-disable;
2884 qup_spi5_cs: qup-spi5-cs-state {
2887 drive-strength = <6>;
2888 bias-disable;
2891 qup_spi5_data_clk: qup-spi5-data-clk-state {
2895 drive-strength = <6>;
2896 bias-disable;
2899 qup_spi6_cs: qup-spi6-cs-state {
2902 drive-strength = <6>;
2903 bias-disable;
2906 qup_spi6_data_clk: qup-spi6-data-clk-state {
2910 drive-strength = <6>;
2911 bias-disable;
2914 qup_spi7_cs: qup-spi7-cs-state {
2917 drive-strength = <6>;
2918 bias-disable;
2921 qup_spi7_data_clk: qup-spi7-data-clk-state {
2925 drive-strength = <6>;
2926 bias-disable;
2929 qup_spi8_cs: qup-spi8-cs-state {
2932 drive-strength = <6>;
2933 bias-disable;
2936 qup_spi8_data_clk: qup-spi8-data-clk-state {
2940 drive-strength = <6>;
2941 bias-disable;
2944 qup_spi9_cs: qup-spi9-cs-state {
2947 drive-strength = <6>;
2948 bias-disable;
2951 qup_spi9_data_clk: qup-spi9-data-clk-state {
2955 drive-strength = <6>;
2956 bias-disable;
2959 qup_spi10_cs: qup-spi10-cs-state {
2962 drive-strength = <6>;
2963 bias-disable;
2966 qup_spi10_data_clk: qup-spi10-data-clk-state {
2970 drive-strength = <6>;
2971 bias-disable;
2974 qup_spi11_cs: qup-spi11-cs-state {
2977 drive-strength = <6>;
2978 bias-disable;
2981 qup_spi11_data_clk: qup-spi11-data-clk-state {
2985 drive-strength = <6>;
2986 bias-disable;
2989 qup_spi12_cs: qup-spi12-cs-state {
2992 drive-strength = <6>;
2993 bias-disable;
2996 qup_spi12_data_clk: qup-spi12-data-clk-state {
3000 drive-strength = <6>;
3001 bias-disable;
3004 qup_spi13_cs: qup-spi13-cs-state {
3007 drive-strength = <6>;
3008 bias-disable;
3011 qup_spi13_data_clk: qup-spi13-data-clk-state {
3015 drive-strength = <6>;
3016 bias-disable;
3019 qup_spi14_cs: qup-spi14-cs-state {
3022 drive-strength = <6>;
3023 bias-disable;
3026 qup_spi14_data_clk: qup-spi14-data-clk-state {
3030 drive-strength = <6>;
3031 bias-disable;
3034 qup_spi15_cs: qup-spi15-cs-state {
3037 drive-strength = <6>;
3038 bias-disable;
3041 qup_spi15_data_clk: qup-spi15-data-clk-state {
3045 drive-strength = <6>;
3046 bias-disable;
3049 qup_spi16_cs: qup-spi16-cs-state {
3052 drive-strength = <6>;
3053 bias-disable;
3056 qup_spi16_data_clk: qup-spi16-data-clk-state {
3060 drive-strength = <6>;
3061 bias-disable;
3064 qup_spi17_cs: qup-spi17-cs-state {
3067 drive-strength = <6>;
3068 bias-disable;
3071 qup_spi17_data_clk: qup-spi17-data-clk-state {
3075 drive-strength = <6>;
3076 bias-disable;
3079 qup_spi18_cs: qup-spi18-cs-state {
3082 drive-strength = <6>;
3083 bias-disable;
3086 qup_spi18_data_clk: qup-spi18-data-clk-state {
3090 drive-strength = <6>;
3091 bias-disable;
3094 qup_spi19_cs: qup-spi19-cs-state {
3097 drive-strength = <6>;
3098 bias-disable;
3101 qup_spi19_data_clk: qup-spi19-data-clk-state {
3105 drive-strength = <6>;
3106 bias-disable;
3109 qup_spi20_cs: qup-spi20-cs-state {
3112 drive-strength = <6>;
3113 bias-disable;
3116 qup_spi20_data_clk: qup-spi20-data-clk-state {
3120 drive-strength = <6>;
3121 bias-disable;
3124 qup_spi21_cs: qup-spi21-cs-state {
3127 drive-strength = <6>;
3128 bias-disable;
3131 qup_spi21_data_clk: qup-spi21-data-clk-state {
3135 drive-strength = <6>;
3136 bias-disable;
3139 qup_spi22_cs: qup-spi22-cs-state {
3142 drive-strength = <6>;
3143 bias-disable;
3146 qup_spi22_data_clk: qup-spi22-data-clk-state {
3150 drive-strength = <6>;
3151 bias-disable;
3154 qup_spi23_cs: qup-spi23-cs-state {
3157 drive-strength = <6>;
3158 bias-disable;
3161 qup_spi23_data_clk: qup-spi23-data-clk-state {
3165 drive-strength = <6>;
3166 bias-disable;
3169 qup_uart21_default: qup-uart21-default-state {
3173 drive-strength= <2>;
3174 bias-disable;
3179 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3280 #iommu-cells = <2>;
3281 #global-interrupts = <1>;
3284 intc: interrupt-controller@17000000 {
3285 compatible = "arm,gic-v3";
3291 #interrupt-cells = <3>;
3292 interrupt-controller;
3294 #redistributor-regions = <1>;
3295 redistributor-stride = <0x0 0x40000>;
3297 #address-cells = <2>;
3298 #size-cells = <2>;
3301 gic_its: msi-controller@17040000 {
3302 compatible = "arm,gic-v3-its";
3305 msi-controller;
3306 #msi-cells = <1>;
3313 compatible = "qcom,rpmh-rsc";
3317 reg-names = "drv-0", "drv-1", "drv-2";
3318 qcom,drv-count = <3>;
3323 qcom,tcs-offset = <0xd00>;
3324 qcom,drv-id = <2>;
3325 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3330 apps_bcm_voter: bcm-voter {
3331 compatible = "qcom,bcm-voter";
3334 rpmhcc: clock-controller {
3335 compatible = "qcom,x1e80100-rpmh-clk";
3338 clock-names = "xo";
3340 #clock-cells = <1>;
3343 rpmhpd: power-controller {
3344 compatible = "qcom,x1e80100-rpmhpd";
3346 operating-points-v2 = <&rpmhpd_opp_table>;
3348 #power-domain-cells = <1>;
3350 rpmhpd_opp_table: opp-table {
3351 compatible = "operating-points-v2";
3353 rpmhpd_opp_ret: opp-16 {
3354 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3357 rpmhpd_opp_min_svs: opp-48 {
3358 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3361 rpmhpd_opp_low_svs_d2: opp-52 {
3362 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3365 rpmhpd_opp_low_svs_d1: opp-56 {
3366 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3369 rpmhpd_opp_low_svs_d0: opp-60 {
3370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3373 rpmhpd_opp_low_svs: opp-64 {
3374 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3377 rpmhpd_opp_low_svs_l1: opp-80 {
3378 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3381 rpmhpd_opp_svs: opp-128 {
3382 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3385 rpmhpd_opp_svs_l0: opp-144 {
3386 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3389 rpmhpd_opp_svs_l1: opp-192 {
3390 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3393 rpmhpd_opp_nom: opp-256 {
3394 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3397 rpmhpd_opp_nom_l1: opp-320 {
3398 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3401 rpmhpd_opp_nom_l2: opp-336 {
3402 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3405 rpmhpd_opp_turbo: opp-384 {
3406 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3409 rpmhpd_opp_turbo_l1: opp-416 {
3410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3417 compatible = "arm,armv7-timer-mem";
3420 #address-cells = <2>;
3421 #size-cells = <1>;
3431 frame-number = <0>;
3439 frame-number = <1>;
3449 frame-number = <2>;
3459 frame-number = <3>;
3469 frame-number = <4>;
3479 frame-number = <5>;
3489 frame-number = <6>;
3495 system-cache-controller@25000000 {
3496 compatible = "qcom,x1e80100-llcc";
3506 reg-names = "llcc0_base",
3520 compatible = "arm,armv8-timer";