Lines Matching +full:spi +full:- +full:qup +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
22 #include <dt-bindings/soc/qcom,gpr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
46 bi_tcxo_div2: bi-tcxo-div2-clk {
47 compatible = "fixed-factor-clock";
48 #clock-cells = <0>;
51 clock-mult = <1>;
52 clock-div = <2>;
55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
56 compatible = "fixed-factor-clock";
57 #clock-cells = <0>;
60 clock-mult = <1>;
61 clock-div = <2>;
64 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
71 #address-cells = <2>;
72 #size-cells = <0>;
76 compatible = "arm,cortex-a520";
81 power-domains = <&CPU_PD0>;
82 power-domain-names = "psci";
84 enable-method = "psci";
85 next-level-cache = <&L2_0>;
86 capacity-dmips-mhz = <1024>;
87 dynamic-power-coefficient = <100>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
91 #cooling-cells = <2>;
93 L2_0: l2-cache {
95 cache-level = <2>;
96 cache-unified;
97 next-level-cache = <&L3_0>;
99 L3_0: l3-cache {
101 cache-level = <3>;
102 cache-unified;
109 compatible = "arm,cortex-a520";
114 power-domains = <&CPU_PD1>;
115 power-domain-names = "psci";
117 enable-method = "psci";
118 next-level-cache = <&L2_0>;
119 capacity-dmips-mhz = <1024>;
120 dynamic-power-coefficient = <100>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
124 #cooling-cells = <2>;
129 compatible = "arm,cortex-a720";
134 power-domains = <&CPU_PD2>;
135 power-domain-names = "psci";
137 enable-method = "psci";
138 next-level-cache = <&L2_200>;
139 capacity-dmips-mhz = <1792>;
140 dynamic-power-coefficient = <238>;
142 qcom,freq-domain = <&cpufreq_hw 3>;
144 #cooling-cells = <2>;
146 L2_200: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
156 compatible = "arm,cortex-a720";
161 power-domains = <&CPU_PD3>;
162 power-domain-names = "psci";
164 enable-method = "psci";
165 next-level-cache = <&L2_200>;
166 capacity-dmips-mhz = <1792>;
167 dynamic-power-coefficient = <238>;
169 qcom,freq-domain = <&cpufreq_hw 3>;
171 #cooling-cells = <2>;
176 compatible = "arm,cortex-a720";
181 power-domains = <&CPU_PD4>;
182 power-domain-names = "psci";
184 enable-method = "psci";
185 next-level-cache = <&L2_400>;
186 capacity-dmips-mhz = <1792>;
187 dynamic-power-coefficient = <238>;
189 qcom,freq-domain = <&cpufreq_hw 3>;
191 #cooling-cells = <2>;
193 L2_400: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&L3_0>;
203 compatible = "arm,cortex-a720";
208 power-domains = <&CPU_PD5>;
209 power-domain-names = "psci";
211 enable-method = "psci";
212 next-level-cache = <&L2_500>;
213 capacity-dmips-mhz = <1792>;
214 dynamic-power-coefficient = <238>;
216 qcom,freq-domain = <&cpufreq_hw 1>;
218 #cooling-cells = <2>;
220 L2_500: l2-cache {
222 cache-level = <2>;
223 cache-unified;
224 next-level-cache = <&L3_0>;
230 compatible = "arm,cortex-a720";
235 power-domains = <&CPU_PD6>;
236 power-domain-names = "psci";
238 enable-method = "psci";
239 next-level-cache = <&L2_600>;
240 capacity-dmips-mhz = <1792>;
241 dynamic-power-coefficient = <238>;
243 qcom,freq-domain = <&cpufreq_hw 1>;
245 #cooling-cells = <2>;
247 L2_600: l2-cache {
249 cache-level = <2>;
250 cache-unified;
251 next-level-cache = <&L3_0>;
257 compatible = "arm,cortex-x4";
262 power-domains = <&CPU_PD7>;
263 power-domain-names = "psci";
265 enable-method = "psci";
266 next-level-cache = <&L2_700>;
267 capacity-dmips-mhz = <1894>;
268 dynamic-power-coefficient = <588>;
270 qcom,freq-domain = <&cpufreq_hw 2>;
272 #cooling-cells = <2>;
274 L2_700: l2-cache {
276 cache-level = <2>;
277 cache-unified;
278 next-level-cache = <&L3_0>;
282 cpu-map {
318 idle-states {
319 entry-method = "psci";
321 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
322 compatible = "arm,idle-state";
323 idle-state-name = "silver-rail-power-collapse";
324 arm,psci-suspend-param = <0x40000004>;
325 entry-latency-us = <550>;
326 exit-latency-us = <750>;
327 min-residency-us = <6700>;
328 local-timer-stop;
331 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
332 compatible = "arm,idle-state";
333 idle-state-name = "gold-rail-power-collapse";
334 arm,psci-suspend-param = <0x40000004>;
335 entry-latency-us = <600>;
336 exit-latency-us = <1300>;
337 min-residency-us = <8136>;
338 local-timer-stop;
341 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
342 compatible = "arm,idle-state";
343 idle-state-name = "gold-plus-rail-power-collapse";
344 arm,psci-suspend-param = <0x40000004>;
345 entry-latency-us = <500>;
346 exit-latency-us = <1350>;
347 min-residency-us = <7480>;
348 local-timer-stop;
352 domain-idle-states {
353 CLUSTER_SLEEP_0: cluster-sleep-0 {
354 compatible = "domain-idle-state";
355 arm,psci-suspend-param = <0x41000044>;
356 entry-latency-us = <750>;
357 exit-latency-us = <2350>;
358 min-residency-us = <9144>;
361 CLUSTER_SLEEP_1: cluster-sleep-1 {
362 compatible = "domain-idle-state";
363 arm,psci-suspend-param = <0x4100c344>;
364 entry-latency-us = <2800>;
365 exit-latency-us = <4400>;
366 min-residency-us = <10150>;
373 compatible = "qcom,scm-sm8650", "qcom,scm";
379 clk_virt: interconnect-0 {
380 compatible = "qcom,sm8650-clk-virt";
381 #interconnect-cells = <2>;
382 qcom,bcm-voters = <&apps_bcm_voter>;
385 mc_virt: interconnect-1 {
386 compatible = "qcom,sm8650-mc-virt";
387 #interconnect-cells = <2>;
388 qcom,bcm-voters = <&apps_bcm_voter>;
398 compatible = "arm,armv8-pmuv3";
403 compatible = "arm,psci-1.0";
406 CPU_PD0: power-domain-cpu0 {
407 #power-domain-cells = <0>;
408 power-domains = <&CLUSTER_PD>;
409 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
412 CPU_PD1: power-domain-cpu1 {
413 #power-domain-cells = <0>;
414 power-domains = <&CLUSTER_PD>;
415 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
418 CPU_PD2: power-domain-cpu2 {
419 #power-domain-cells = <0>;
420 power-domains = <&CLUSTER_PD>;
421 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
424 CPU_PD3: power-domain-cpu3 {
425 #power-domain-cells = <0>;
426 power-domains = <&CLUSTER_PD>;
427 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
430 CPU_PD4: power-domain-cpu4 {
431 #power-domain-cells = <0>;
432 power-domains = <&CLUSTER_PD>;
433 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
436 CPU_PD5: power-domain-cpu5 {
437 #power-domain-cells = <0>;
438 power-domains = <&CLUSTER_PD>;
439 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
442 CPU_PD6: power-domain-cpu6 {
443 #power-domain-cells = <0>;
444 power-domains = <&CLUSTER_PD>;
445 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
448 CPU_PD7: power-domain-cpu7 {
449 #power-domain-cells = <0>;
450 power-domains = <&CLUSTER_PD>;
451 domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
454 CLUSTER_PD: power-domain-cluster {
455 #power-domain-cells = <0>;
456 domain-idle-states = <&CLUSTER_SLEEP_0>,
461 reserved_memory: reserved-memory {
462 #address-cells = <2>;
463 #size-cells = <2>;
468 no-map;
471 cpusys_vm_mem: cpusys-vm@80e00000 {
473 no-map;
477 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
479 no-map;
482 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd-db";
485 no-map;
489 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
491 no-map;
500 no-map;
503 adsp_mhi_mem: adsp-mhi@81f00000 {
505 no-map;
510 no-map;
513 global_sync_mem: global-sync@82600000 {
515 no-map;
518 tz_stat_mem: tz-stat@82700000 {
520 no-map;
525 no-map;
528 mpss_dsm_mem: mpss-dsm@86b00000 {
530 no-map;
533 mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
535 no-map;
540 no-map;
543 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
545 no-map;
548 ipa_fw_mem: ipa-fw@9b080000 {
550 no-map;
553 ipa_gsi_mem: ipa-gsi@9b090000 {
555 no-map;
558 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
560 no-map;
565 no-map;
569 spu_tz_shared_mem: spu-tz-shared@9b280000 {
571 no-map;
575 spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
577 no-map;
582 no-map;
587 no-map;
592 no-map;
597 no-map;
600 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
602 no-map;
605 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
607 no-map;
612 no-map;
616 compatible = "qcom,rmtfs-mem";
618 no-map;
620 qcom,client-id = <1>;
625 tz_merged_mem: tz-merged@d8000000 {
627 no-map;
630 hwfence_shbuf: hwfence-shbuf@e6440000 {
632 no-map;
635 trust_ui_vm_mem: trust-ui-vm@f3800000 {
637 no-map;
640 oem_vm_mem: oem-vm@f7c00000 {
642 no-map;
645 llcc_lpi_mem: llcc-lpi@ff800000 {
647 no-map;
651 smp2p-adsp {
654 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
662 qcom,local-pid = <0>;
663 qcom,remote-pid = <2>;
665 smp2p_adsp_out: master-kernel {
666 qcom,entry-name = "master-kernel";
667 #qcom,smem-state-cells = <1>;
670 smp2p_adsp_in: slave-kernel {
671 qcom,entry-name = "slave-kernel";
672 interrupt-controller;
673 #interrupt-cells = <2>;
677 smp2p-cdsp {
680 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
688 qcom,local-pid = <0>;
689 qcom,remote-pid = <5>;
691 smp2p_cdsp_out: master-kernel {
692 qcom,entry-name = "master-kernel";
693 #qcom,smem-state-cells = <1>;
696 smp2p_cdsp_in: slave-kernel {
697 qcom,entry-name = "slave-kernel";
698 interrupt-controller;
699 #interrupt-cells = <2>;
703 smp2p-modem {
706 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
714 qcom,local-pid = <0>;
715 qcom,remote-pid = <1>;
717 smp2p_modem_out: master-kernel {
718 qcom,entry-name = "master-kernel";
719 #qcom,smem-state-cells = <1>;
722 smp2p_modem_in: slave-kernel {
723 qcom,entry-name = "slave-kernel";
724 interrupt-controller;
725 #interrupt-cells = <2>;
728 ipa_smp2p_out: ipa-ap-to-modem {
729 qcom,entry-name = "ipa";
730 #qcom,smem-state-cells = <1>;
733 ipa_smp2p_in: ipa-modem-to-ap {
734 qcom,entry-name = "ipa";
735 interrupt-controller;
736 #interrupt-cells = <2>;
741 compatible = "simple-bus";
743 #address-cells = <2>;
744 #size-cells = <2>;
745 dma-ranges = <0 0 0 0 0x10 0>;
748 gcc: clock-controller@100000 {
749 compatible = "qcom,sm8650-gcc";
763 #clock-cells = <1>;
764 #reset-cells = <1>;
765 #power-domain-cells = <1>;
769 compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
773 interrupt-controller;
774 #interrupt-cells = <3>;
776 #mbox-cells = <2>;
779 gpi_dma2: dma-controller@800000 {
780 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
796 dma-channels = <12>;
797 dma-channel-mask = <0x3f>;
798 #dma-cells = <3>;
802 dma-coherent;
808 compatible = "qcom,geni-se-qup";
813 clock-names = "m-ahb",
814 "s-ahb";
818 dma-coherent;
820 #address-cells = <2>;
821 #size-cells = <2>;
827 compatible = "qcom,geni-i2c";
833 clock-names = "se";
841 interconnect-names = "qup-core",
842 "qup-config",
843 "qup-memory";
847 dma-names = "tx",
850 pinctrl-0 = <&qup_i2c8_data_clk>;
851 pinctrl-names = "default";
853 #address-cells = <1>;
854 #size-cells = <0>;
859 spi8: spi@880000 {
860 compatible = "qcom,geni-spi";
866 clock-names = "se";
874 interconnect-names = "qup-core",
875 "qup-config",
876 "qup-memory";
880 dma-names = "tx",
883 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
884 pinctrl-names = "default";
886 #address-cells = <1>;
887 #size-cells = <0>;
893 compatible = "qcom,geni-i2c";
899 clock-names = "se";
907 interconnect-names = "qup-core",
908 "qup-config",
909 "qup-memory";
913 dma-names = "tx",
916 pinctrl-0 = <&qup_i2c9_data_clk>;
917 pinctrl-names = "default";
919 #address-cells = <1>;
920 #size-cells = <0>;
925 spi9: spi@884000 {
926 compatible = "qcom,geni-spi";
932 clock-names = "se";
940 interconnect-names = "qup-core",
941 "qup-config",
942 "qup-memory";
946 dma-names = "tx",
949 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
950 pinctrl-names = "default";
952 #address-cells = <1>;
953 #size-cells = <0>;
959 compatible = "qcom,geni-i2c";
965 clock-names = "se";
973 interconnect-names = "qup-core",
974 "qup-config",
975 "qup-memory";
979 dma-names = "tx",
982 pinctrl-0 = <&qup_i2c10_data_clk>;
983 pinctrl-names = "default";
985 #address-cells = <1>;
986 #size-cells = <0>;
991 spi10: spi@888000 {
992 compatible = "qcom,geni-spi";
998 clock-names = "se";
1006 interconnect-names = "qup-core",
1007 "qup-config",
1008 "qup-memory";
1012 dma-names = "tx",
1015 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1016 pinctrl-names = "default";
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1025 compatible = "qcom,geni-i2c";
1031 clock-names = "se";
1039 interconnect-names = "qup-core",
1040 "qup-config",
1041 "qup-memory";
1045 dma-names = "tx",
1048 pinctrl-0 = <&qup_i2c11_data_clk>;
1049 pinctrl-names = "default";
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1057 spi11: spi@88c000 {
1058 compatible = "qcom,geni-spi";
1064 clock-names = "se";
1072 interconnect-names = "qup-core",
1073 "qup-config",
1074 "qup-memory";
1078 dma-names = "tx",
1081 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1082 pinctrl-names = "default";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1091 compatible = "qcom,geni-i2c";
1097 clock-names = "se";
1105 interconnect-names = "qup-core",
1106 "qup-config",
1107 "qup-memory";
1111 dma-names = "tx",
1114 pinctrl-0 = <&qup_i2c12_data_clk>;
1115 pinctrl-names = "default";
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1123 spi12: spi@890000 {
1124 compatible = "qcom,geni-spi";
1130 clock-names = "se";
1138 interconnect-names = "qup-core",
1139 "qup-config",
1140 "qup-memory";
1144 dma-names = "tx",
1147 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1148 pinctrl-names = "default";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1157 compatible = "qcom,geni-i2c";
1163 clock-names = "se";
1171 interconnect-names = "qup-core",
1172 "qup-config",
1173 "qup-memory";
1177 dma-names = "tx",
1180 pinctrl-0 = <&qup_i2c13_data_clk>;
1181 pinctrl-names = "default";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1189 spi13: spi@894000 {
1190 compatible = "qcom,geni-spi";
1196 clock-names = "se";
1204 interconnect-names = "qup-core",
1205 "qup-config",
1206 "qup-memory";
1210 dma-names = "tx",
1213 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1214 pinctrl-names = "default";
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1223 compatible = "qcom,geni-uart";
1229 clock-names = "se";
1235 interconnect-names = "qup-core",
1236 "qup-config";
1238 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1239 pinctrl-names = "default";
1245 compatible = "qcom,geni-debug-uart";
1251 clock-names = "se";
1257 interconnect-names = "qup-core",
1258 "qup-config";
1260 pinctrl-0 = <&qup_uart15_default>;
1261 pinctrl-names = "default";
1268 compatible = "qcom,geni-se-i2c-master-hub";
1272 clock-names = "s-ahb";
1274 #address-cells = <2>;
1275 #size-cells = <2>;
1281 compatible = "qcom,geni-i2c-master-hub";
1288 clock-names = "se",
1295 interconnect-names = "qup-core",
1296 "qup-config";
1298 pinctrl-0 = <&hub_i2c0_data_clk>;
1299 pinctrl-names = "default";
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1308 compatible = "qcom,geni-i2c-master-hub";
1315 clock-names = "se",
1322 interconnect-names = "qup-core",
1323 "qup-config";
1325 pinctrl-0 = <&hub_i2c1_data_clk>;
1326 pinctrl-names = "default";
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1335 compatible = "qcom,geni-i2c-master-hub";
1342 clock-names = "se",
1349 interconnect-names = "qup-core",
1350 "qup-config";
1352 pinctrl-0 = <&hub_i2c2_data_clk>;
1353 pinctrl-names = "default";
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1362 compatible = "qcom,geni-i2c-master-hub";
1369 clock-names = "se",
1376 interconnect-names = "qup-core",
1377 "qup-config";
1379 pinctrl-0 = <&hub_i2c3_data_clk>;
1380 pinctrl-names = "default";
1382 #address-cells = <1>;
1383 #size-cells = <0>;
1389 compatible = "qcom,geni-i2c-master-hub";
1396 clock-names = "se",
1403 interconnect-names = "qup-core",
1404 "qup-config";
1406 pinctrl-0 = <&hub_i2c4_data_clk>;
1407 pinctrl-names = "default";
1409 #address-cells = <1>;
1410 #size-cells = <0>;
1416 compatible = "qcom,geni-i2c-master-hub";
1423 clock-names = "se",
1430 interconnect-names = "qup-core",
1431 "qup-config";
1433 pinctrl-0 = <&hub_i2c5_data_clk>;
1434 pinctrl-names = "default";
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1443 compatible = "qcom,geni-i2c-master-hub";
1450 clock-names = "se",
1457 interconnect-names = "qup-core",
1458 "qup-config";
1460 pinctrl-0 = <&hub_i2c6_data_clk>;
1461 pinctrl-names = "default";
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1470 compatible = "qcom,geni-i2c-master-hub";
1477 clock-names = "se",
1484 interconnect-names = "qup-core",
1485 "qup-config";
1487 pinctrl-0 = <&hub_i2c7_data_clk>;
1488 pinctrl-names = "default";
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1497 compatible = "qcom,geni-i2c-master-hub";
1504 clock-names = "se",
1511 interconnect-names = "qup-core",
1512 "qup-config";
1514 pinctrl-0 = <&hub_i2c8_data_clk>;
1515 pinctrl-names = "default";
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1524 compatible = "qcom,geni-i2c-master-hub";
1531 clock-names = "se",
1538 interconnect-names = "qup-core",
1539 "qup-config";
1541 pinctrl-0 = <&hub_i2c9_data_clk>;
1542 pinctrl-names = "default";
1544 #address-cells = <1>;
1545 #size-cells = <0>;
1551 gpi_dma1: dma-controller@a00000 {
1552 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
1568 dma-channels = <12>;
1569 dma-channel-mask = <0xc>;
1570 #dma-cells = <3>;
1573 dma-coherent;
1579 compatible = "qcom,geni-se-qup";
1584 clock-names = "m-ahb",
1585 "s-ahb";
1589 interconnect-names = "qup-core";
1593 dma-coherent;
1595 #address-cells = <2>;
1596 #size-cells = <2>;
1602 compatible = "qcom,geni-i2c";
1608 clock-names = "se";
1616 interconnect-names = "qup-core",
1617 "qup-config",
1618 "qup-memory";
1622 dma-names = "tx",
1625 pinctrl-0 = <&qup_i2c0_data_clk>;
1626 pinctrl-names = "default";
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1634 spi0: spi@a80000 {
1635 compatible = "qcom,geni-spi";
1641 clock-names = "se";
1649 interconnect-names = "qup-core",
1650 "qup-config",
1651 "qup-memory";
1655 dma-names = "tx",
1658 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1659 pinctrl-names = "default";
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1668 compatible = "qcom,geni-i2c";
1674 clock-names = "se";
1682 interconnect-names = "qup-core",
1683 "qup-config",
1684 "qup-memory";
1688 dma-names = "tx",
1691 pinctrl-0 = <&qup_i2c1_data_clk>;
1692 pinctrl-names = "default";
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1700 spi1: spi@a84000 {
1701 compatible = "qcom,geni-spi";
1707 clock-names = "se";
1715 interconnect-names = "qup-core",
1716 "qup-config",
1717 "qup-memory";
1721 dma-names = "tx",
1724 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1725 pinctrl-names = "default";
1727 #address-cells = <1>;
1728 #size-cells = <0>;
1734 compatible = "qcom,geni-i2c";
1740 clock-names = "se";
1748 interconnect-names = "qup-core",
1749 "qup-config",
1750 "qup-memory";
1754 dma-names = "tx",
1757 pinctrl-0 = <&qup_i2c2_data_clk>;
1758 pinctrl-names = "default";
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1766 spi2: spi@a88000 {
1767 compatible = "qcom,geni-spi";
1773 clock-names = "se";
1781 interconnect-names = "qup-core",
1782 "qup-config",
1783 "qup-memory";
1787 dma-names = "tx",
1790 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1791 pinctrl-names = "default";
1793 #address-cells = <1>;
1794 #size-cells = <0>;
1800 compatible = "qcom,geni-i2c";
1806 clock-names = "se";
1814 interconnect-names = "qup-core",
1815 "qup-config",
1816 "qup-memory";
1820 dma-names = "tx",
1823 pinctrl-0 = <&qup_i2c3_data_clk>;
1824 pinctrl-names = "default";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1832 spi3: spi@a8c000 {
1833 compatible = "qcom,geni-spi";
1839 clock-names = "se";
1847 interconnect-names = "qup-core",
1848 "qup-config",
1849 "qup-memory";
1853 dma-names = "tx",
1856 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1857 pinctrl-names = "default";
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1866 compatible = "qcom,geni-i2c";
1872 clock-names = "se";
1880 interconnect-names = "qup-core",
1881 "qup-config",
1882 "qup-memory";
1886 dma-names = "tx",
1889 pinctrl-0 = <&qup_i2c4_data_clk>;
1890 pinctrl-names = "default";
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1898 spi4: spi@a90000 {
1899 compatible = "qcom,geni-spi";
1905 clock-names = "se";
1913 interconnect-names = "qup-core",
1914 "qup-config",
1915 "qup-memory";
1919 dma-names = "tx",
1922 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1923 pinctrl-names = "default";
1925 #address-cells = <1>;
1926 #size-cells = <0>;
1932 compatible = "qcom,geni-i2c";
1938 clock-names = "se";
1946 interconnect-names = "qup-core",
1947 "qup-config",
1948 "qup-memory";
1952 dma-names = "tx",
1955 pinctrl-0 = <&qup_i2c5_data_clk>;
1956 pinctrl-names = "default";
1958 #address-cells = <1>;
1959 #size-cells = <0>;
1964 spi5: spi@a94000 {
1965 compatible = "qcom,geni-spi";
1971 clock-names = "se";
1979 interconnect-names = "qup-core",
1980 "qup-config",
1981 "qup-memory";
1985 dma-names = "tx",
1988 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1989 pinctrl-names = "default";
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1998 compatible = "qcom,geni-i2c";
2004 clock-names = "se";
2012 interconnect-names = "qup-core",
2013 "qup-config",
2014 "qup-memory";
2018 dma-names = "tx",
2021 pinctrl-0 = <&qup_i2c6_data_clk>;
2022 pinctrl-names = "default";
2024 #address-cells = <1>;
2025 #size-cells = <0>;
2030 spi6: spi@a98000 {
2031 compatible = "qcom,geni-spi";
2037 clock-names = "se";
2045 interconnect-names = "qup-core",
2046 "qup-config",
2047 "qup-memory";
2051 dma-names = "tx",
2054 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2055 pinctrl-names = "default";
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2064 compatible = "qcom,geni-i2c";
2070 clock-names = "se";
2078 interconnect-names = "qup-core",
2079 "qup-config",
2080 "qup-memory";
2084 dma-names = "tx",
2087 pinctrl-0 = <&qup_i2c7_data_clk>;
2088 pinctrl-names = "default";
2090 #address-cells = <1>;
2091 #size-cells = <0>;
2096 spi7: spi@a9c000 {
2097 compatible = "qcom,geni-spi";
2103 clock-names = "se";
2111 interconnect-names = "qup-core",
2112 "qup-config",
2113 "qup-memory";
2117 dma-names = "tx",
2120 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2121 pinctrl-names = "default";
2123 #address-cells = <1>;
2124 #size-cells = <0>;
2131 compatible = "qcom,sm8650-cnoc-main";
2134 qcom,bcm-voters = <&apps_bcm_voter>;
2136 #interconnect-cells = <2>;
2140 compatible = "qcom,sm8650-config-noc";
2143 qcom,bcm-voters = <&apps_bcm_voter>;
2145 #interconnect-cells = <2>;
2149 compatible = "qcom,sm8650-system-noc";
2152 qcom,bcm-voters = <&apps_bcm_voter>;
2154 #interconnect-cells = <2>;
2158 compatible = "qcom,sm8650-pcie-anoc";
2164 qcom,bcm-voters = <&apps_bcm_voter>;
2166 #interconnect-cells = <2>;
2170 compatible = "qcom,sm8650-aggre1-noc";
2176 qcom,bcm-voters = <&apps_bcm_voter>;
2178 #interconnect-cells = <2>;
2182 compatible = "qcom,sm8650-aggre2-noc";
2187 qcom,bcm-voters = <&apps_bcm_voter>;
2189 #interconnect-cells = <2>;
2193 compatible = "qcom,sm8650-mmss-noc";
2196 qcom,bcm-voters = <&apps_bcm_voter>;
2198 #interconnect-cells = <2>;
2202 compatible = "qcom,sm8650-trng", "qcom,trng";
2208 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2214 reg-names = "parf", "dbi", "elbi", "atu", "config";
2217 interrupt-names = "msi";
2227 clock-names = "aux",
2237 reset-names = "pci";
2243 interconnect-names = "pcie-mem",
2244 "cpu-pcie";
2246 power-domains = <&gcc PCIE_0_GDSC>;
2248 iommu-map = <0 &apps_smmu 0x1400 0x1>,
2251 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2255 interrupt-map-mask = <0 0 0 0x7>;
2256 #interrupt-cells = <1>;
2258 linux,pci-domain = <0>;
2259 num-lanes = <2>;
2260 bus-range = <0 0xff>;
2263 phy-names = "pciephy";
2265 #address-cells = <3>;
2266 #size-cells = <2>;
2270 dma-coherent;
2276 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
2284 clock-names = "aux",
2290 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2291 assigned-clock-rates = <100000000>;
2294 reset-names = "phy";
2296 power-domains = <&gcc PCIE_0_PHY_GDSC>;
2298 #clock-cells = <0>;
2299 clock-output-names = "pcie0_pipe_clk";
2301 #phy-cells = <0>;
2308 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2314 reg-names = "parf",
2321 interrupt-names = "msi";
2331 clock-names = "aux",
2340 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2341 assigned-clock-rates = <19200000>;
2345 reset-names = "pci",
2352 interconnect-names = "pcie-mem",
2353 "cpu-pcie";
2355 power-domains = <&gcc PCIE_1_GDSC>;
2357 iommu-map = <0 &apps_smmu 0x1480 0x1>,
2360 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2364 interrupt-map-mask = <0 0 0 0x7>;
2365 #interrupt-cells = <1>;
2367 linux,pci-domain = <1>;
2368 num-lanes = <2>;
2369 bus-range = <0 0xff>;
2372 phy-names = "pciephy";
2374 dma-coherent;
2376 #address-cells = <3>;
2377 #size-cells = <2>;
2385 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
2393 clock-names = "aux",
2399 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2400 assigned-clock-rates = <100000000>;
2404 reset-names = "phy",
2407 power-domains = <&gcc PCIE_1_PHY_GDSC>;
2409 #clock-cells = <0>;
2410 clock-output-names = "pcie1_pipe_clk";
2412 #phy-cells = <0>;
2417 cryptobam: dma-controller@1dc4000 {
2418 compatible = "qcom,bam-v1.7.0";
2423 #dma-cells = <1>;
2429 qcom,controlled-remotely;
2433 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
2438 interconnect-names = "memory";
2441 dma-names = "rx", "tx";
2448 compatible = "qcom,sm8650-qmp-ufs-phy";
2453 clock-names = "ref",
2457 reset-names = "ufsphy";
2459 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
2461 #clock-cells = <1>;
2462 #phy-cells = <0>;
2468 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2481 clock-names = "core_clk",
2489 freq-table-hz = <100000000 403000000>,
2499 reset-names = "rst";
2505 interconnect-names = "ufs-ddr",
2506 "cpu-ufs";
2508 power-domains = <&gcc UFS_PHY_GDSC>;
2509 required-opps = <&rpmhpd_opp_nom>;
2513 lanes-per-direction = <2>;
2517 phy-names = "ufsphy";
2519 #reset-cells = <1>;
2525 compatible = "qcom,sm8650-inline-crypto-engine",
2526 "qcom,inline-crypto-engine";
2533 compatible = "qcom,tcsr-mutex";
2536 #hwlock-cells = <1>;
2539 tcsr: clock-controller@1fc0000 {
2540 compatible = "qcom,sm8650-tcsr", "syscon";
2545 #clock-cells = <1>;
2546 #reset-cells = <1>;
2549 gpucc: clock-controller@3d90000 {
2550 compatible = "qcom,sm8650-gpucc";
2557 #clock-cells = <1>;
2558 #reset-cells = <1>;
2559 #power-domain-cells = <1>;
2563 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
2570 reg-names = "ipa-reg",
2571 "ipa-shared",
2574 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2578 interrupt-names = "ipa",
2580 "ipa-clock-query",
2581 "ipa-setup-ready";
2584 clock-names = "core";
2588 interconnect-names = "memory",
2593 qcom,smem-states = <&ipa_smp2p_out 0>,
2595 qcom,smem-state-names = "ipa-clock-enabled-valid",
2596 "ipa-clock-enabled";
2602 compatible = "qcom,sm8650-mpss-pas";
2605 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2611 interrupt-names = "wdog",
2615 "stop-ack",
2616 "shutdown-ack";
2619 clock-names = "xo";
2624 power-domains = <&rpmhpd RPMHPD_CX>,
2626 power-domain-names = "cx",
2629 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
2634 qcom,smem-states = <&smp2p_modem_out 0>;
2635 qcom,smem-state-names = "stop";
2639 glink-edge {
2640 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2647 qcom,remote-pid = <1>;
2654 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2660 clock-names = "mclk",
2665 #clock-cells = <0>;
2666 clock-output-names = "wsa2-mclk";
2667 #sound-dai-cells = <1>;
2671 compatible = "qcom,soundwire-v2.0.0";
2675 clock-names = "iface";
2678 pinctrl-0 = <&wsa2_swr_active>;
2679 pinctrl-names = "default";
2681 qcom,din-ports = <4>;
2682 qcom,dout-ports = <9>;
2684 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2685 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2686 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2687 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2688 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2689 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2690 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2691 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2692 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2694 #address-cells = <2>;
2695 #size-cells = <0>;
2696 #sound-dai-cells = <1>;
2701 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
2707 clock-names = "mclk",
2712 #clock-cells = <0>;
2713 clock-output-names = "mclk";
2714 #sound-dai-cells = <1>;
2718 compatible = "qcom,soundwire-v2.0.0";
2722 clock-names = "iface";
2725 pinctrl-0 = <&rx_swr_active>;
2726 pinctrl-names = "default";
2728 qcom,din-ports = <0>;
2729 qcom,dout-ports = <11>;
2731 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
2732 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
2733 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2734 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
2735 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
2736 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
2737 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
2738 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
2739 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2741 #address-cells = <2>;
2742 #size-cells = <0>;
2743 #sound-dai-cells = <1>;
2748 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
2754 clock-names = "mclk",
2759 #clock-cells = <0>;
2760 clock-output-names = "mclk";
2761 #sound-dai-cells = <1>;
2765 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2771 clock-names = "mclk",
2776 #clock-cells = <0>;
2777 clock-output-names = "mclk";
2778 #sound-dai-cells = <1>;
2782 compatible = "qcom,soundwire-v2.0.0";
2786 clock-names = "iface";
2789 pinctrl-0 = <&wsa_swr_active>;
2790 pinctrl-names = "default";
2792 qcom,din-ports = <4>;
2793 qcom,dout-ports = <9>;
2795 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2796 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2797 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2798 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2799 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2800 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2801 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2802 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2803 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2805 #address-cells = <2>;
2806 #size-cells = <0>;
2807 #sound-dai-cells = <1>;
2812 compatible = "qcom,soundwire-v2.0.0";
2816 interrupt-names = "core", "wakeup";
2818 clock-names = "iface";
2821 pinctrl-0 = <&tx_swr_active>;
2822 pinctrl-names = "default";
2824 qcom,din-ports = <4>;
2825 qcom,dout-ports = <0>;
2827 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2828 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2829 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2830 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2831 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2832 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2833 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2834 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2835 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2837 #address-cells = <2>;
2838 #size-cells = <0>;
2839 #sound-dai-cells = <1>;
2844 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
2849 clock-names = "mclk",
2853 #clock-cells = <0>;
2854 clock-output-names = "fsgen";
2855 #sound-dai-cells = <1>;
2859 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
2864 clock-names = "core", "audio";
2866 gpio-controller;
2867 #gpio-cells = <2>;
2868 gpio-ranges = <&lpass_tlmm 0 0 23>;
2870 tx_swr_active: tx-swr-active-state {
2871 clk-pins {
2874 drive-strength = <2>;
2875 slew-rate = <1>;
2876 bias-disable;
2879 data-pins {
2882 drive-strength = <2>;
2883 slew-rate = <1>;
2884 bias-bus-hold;
2888 rx_swr_active: rx-swr-active-state {
2889 clk-pins {
2892 drive-strength = <2>;
2893 slew-rate = <1>;
2894 bias-disable;
2897 data-pins {
2900 drive-strength = <2>;
2901 slew-rate = <1>;
2902 bias-bus-hold;
2906 dmic01_default: dmic01-default-state {
2907 clk-pins {
2910 drive-strength = <8>;
2911 output-high;
2914 data-pins {
2917 drive-strength = <8>;
2918 input-enable;
2922 dmic02_default: dmic02-default-state {
2923 clk-pins {
2926 drive-strength = <8>;
2927 output-high;
2930 data-pins {
2933 drive-strength = <8>;
2934 input-enable;
2938 wsa_swr_active: wsa-swr-active-state {
2939 clk-pins {
2942 drive-strength = <2>;
2943 slew-rate = <1>;
2944 bias-disable;
2947 data-pins {
2950 drive-strength = <2>;
2951 slew-rate = <1>;
2952 bias-bus-hold;
2956 wsa2_swr_active: wsa2-swr-active-state {
2957 clk-pins {
2960 drive-strength = <2>;
2961 slew-rate = <1>;
2962 bias-disable;
2965 data-pins {
2968 drive-strength = <2>;
2969 slew-rate = <1>;
2970 bias-bus-hold;
2976 compatible = "qcom,sm8650-lpass-lpiaon-noc";
2979 #interconnect-cells = <2>;
2981 qcom,bcm-voters = <&apps_bcm_voter>;
2985 compatible = "qcom,sm8650-lpass-lpicx-noc";
2988 #interconnect-cells = <2>;
2990 qcom,bcm-voters = <&apps_bcm_voter>;
2994 compatible = "qcom,sm8650-lpass-ag-noc";
2997 #interconnect-cells = <2>;
2999 qcom,bcm-voters = <&apps_bcm_voter>;
3003 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
3008 interrupt-names = "hc_irq",
3014 clock-names = "iface",
3022 interconnect-names = "sdhc-ddr",
3023 "cpu-sdhc";
3025 power-domains = <&rpmhpd RPMHPD_CX>;
3026 operating-points-v2 = <&sdhc2_opp_table>;
3030 bus-width = <4>;
3032 /* Forbid SDR104/SDR50 - broken hw! */
3033 sdhci-caps-mask = <0x3 0>;
3035 qcom,dll-config = <0x0007642c>;
3036 qcom,ddr-config = <0x80040868>;
3038 dma-coherent;
3042 sdhc2_opp_table: opp-table {
3043 compatible = "operating-points-v2";
3045 opp-19200000 {
3046 opp-hz = /bits/ 64 <19200000>;
3047 required-opps = <&rpmhpd_opp_min_svs>;
3050 opp-50000000 {
3051 opp-hz = /bits/ 64 <50000000>;
3052 required-opps = <&rpmhpd_opp_low_svs>;
3055 opp-100000000 {
3056 opp-hz = /bits/ 64 <100000000>;
3057 required-opps = <&rpmhpd_opp_svs>;
3060 opp-202000000 {
3061 opp-hz = /bits/ 64 <202000000>;
3062 required-opps = <&rpmhpd_opp_svs_l1>;
3067 mdss: display-subsystem@ae00000 {
3068 compatible = "qcom,sm8650-mdss";
3070 reg-names = "mdss";
3084 interconnect-names = "mdp0-mem",
3085 "mdp1-mem";
3087 power-domains = <&dispcc MDSS_GDSC>;
3091 interrupt-controller;
3092 #interrupt-cells = <1>;
3094 #address-cells = <2>;
3095 #size-cells = <2>;
3100 mdss_mdp: display-controller@ae01000 {
3101 compatible = "qcom,sm8650-dpu";
3104 reg-names = "mdp",
3107 interrupts-extended = <&mdss 0>;
3114 clock-names = "nrt_bus",
3120 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3121 assigned-clock-rates = <19200000>;
3123 operating-points-v2 = <&mdp_opp_table>;
3125 power-domains = <&rpmhpd RPMHPD_MMCX>;
3128 #address-cells = <1>;
3129 #size-cells = <0>;
3135 remote-endpoint = <&mdss_dsi0_in>;
3143 remote-endpoint = <&mdss_dsi1_in>;
3151 remote-endpoint = <&mdss_dp0_in>;
3156 mdp_opp_table: opp-table {
3157 compatible = "operating-points-v2";
3159 opp-200000000 {
3160 opp-hz = /bits/ 64 <200000000>;
3161 required-opps = <&rpmhpd_opp_low_svs>;
3164 opp-325000000 {
3165 opp-hz = /bits/ 64 <325000000>;
3166 required-opps = <&rpmhpd_opp_svs>;
3169 opp-375000000 {
3170 opp-hz = /bits/ 64 <375000000>;
3171 required-opps = <&rpmhpd_opp_svs_l1>;
3174 opp-514000000 {
3175 opp-hz = /bits/ 64 <514000000>;
3176 required-opps = <&rpmhpd_opp_nom>;
3182 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3184 reg-names = "dsi_ctrl";
3186 interrupts-extended = <&mdss 4>;
3194 clock-names = "byte",
3201 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3203 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3206 operating-points-v2 = <&mdss_dsi_opp_table>;
3208 power-domains = <&rpmhpd RPMHPD_MMCX>;
3211 phy-names = "dsi";
3213 #address-cells = <1>;
3214 #size-cells = <0>;
3219 #address-cells = <1>;
3220 #size-cells = <0>;
3226 remote-endpoint = <&dpu_intf1_out>;
3238 mdss_dsi_opp_table: opp-table {
3239 compatible = "operating-points-v2";
3241 opp-187500000 {
3242 opp-hz = /bits/ 64 <187500000>;
3243 required-opps = <&rpmhpd_opp_low_svs>;
3246 opp-300000000 {
3247 opp-hz = /bits/ 64 <300000000>;
3248 required-opps = <&rpmhpd_opp_svs>;
3251 opp-358000000 {
3252 opp-hz = /bits/ 64 <358000000>;
3253 required-opps = <&rpmhpd_opp_svs_l1>;
3259 compatible = "qcom,sm8650-dsi-phy-4nm";
3263 reg-names = "dsi_phy",
3269 clock-names = "iface",
3272 #clock-cells = <1>;
3273 #phy-cells = <0>;
3279 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3281 reg-names = "dsi_ctrl";
3283 interrupts-extended = <&mdss 5>;
3291 clock-names = "byte",
3298 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3300 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3303 operating-points-v2 = <&mdss_dsi_opp_table>;
3305 power-domains = <&rpmhpd RPMHPD_MMCX>;
3308 phy-names = "dsi";
3310 #address-cells = <1>;
3311 #size-cells = <0>;
3316 #address-cells = <1>;
3317 #size-cells = <0>;
3323 remote-endpoint = <&dpu_intf2_out>;
3337 compatible = "qcom,sm8650-dsi-phy-4nm";
3341 reg-names = "dsi_phy",
3347 clock-names = "iface",
3350 #clock-cells = <1>;
3351 #phy-cells = <0>;
3356 mdss_dp0: displayport-controller@af54000 {
3357 compatible = "qcom,sm8650-dp";
3364 interrupts-extended = <&mdss 12>;
3371 clock-names = "core_iface",
3377 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3379 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3382 operating-points-v2 = <&dp_opp_table>;
3384 power-domains = <&rpmhpd RPMHPD_MMCX>;
3387 phy-names = "dp";
3389 #sound-dai-cells = <0>;
3393 dp_opp_table: opp-table {
3394 compatible = "operating-points-v2";
3396 opp-162000000 {
3397 opp-hz = /bits/ 64 <162000000>;
3398 required-opps = <&rpmhpd_opp_low_svs_d1>;
3401 opp-270000000 {
3402 opp-hz = /bits/ 64 <270000000>;
3403 required-opps = <&rpmhpd_opp_low_svs>;
3406 opp-540000000 {
3407 opp-hz = /bits/ 64 <540000000>;
3408 required-opps = <&rpmhpd_opp_svs_l1>;
3411 opp-810000000 {
3412 opp-hz = /bits/ 64 <810000000>;
3413 required-opps = <&rpmhpd_opp_nom>;
3418 #address-cells = <1>;
3419 #size-cells = <0>;
3425 remote-endpoint = <&dpu_intf0_out>;
3439 dispcc: clock-controller@af00000 {
3440 compatible = "qcom,sm8650-dispcc";
3460 power-domains = <&rpmhpd RPMHPD_MMCX>;
3461 required-opps = <&rpmhpd_opp_low_svs>;
3463 #clock-cells = <1>;
3464 #reset-cells = <1>;
3465 #power-domain-cells = <1>;
3471 compatible = "qcom,sm8650-snps-eusb2-phy",
3472 "qcom,sm8550-snps-eusb2-phy";
3476 clock-names = "ref";
3480 #phy-cells = <0>;
3486 compatible = "qcom,sm8650-qmp-usb3-dp-phy";
3493 clock-names = "aux",
3500 reset-names = "phy",
3503 power-domains = <&gcc USB3_PHY_GDSC>;
3505 #clock-cells = <1>;
3506 #phy-cells = <1>;
3511 #address-cells = <1>;
3512 #size-cells = <0>;
3538 compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
3541 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3545 interrupt-names = "hs_phy_irq",
3556 clock-names = "cfg_noc",
3563 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3565 assigned-clock-rates = <19200000>, <200000000>;
3569 power-domains = <&gcc USB30_PRIM_GDSC>;
3570 required-opps = <&rpmhpd_opp_nom>;
3572 #address-cells = <2>;
3573 #size-cells = <2>;
3588 phy-names = "usb2-phy",
3589 "usb3-phy";
3591 snps,hird-threshold = /bits/ 8 <0x0>;
3592 snps,usb2-gadget-lpm-disable;
3595 snps,dis-u1-entry-quirk;
3596 snps,dis-u2-entry-quirk;
3597 snps,is-utmi-l1-suspend;
3599 snps,usb2-lpm-disable;
3600 snps,has-lpm-erratum;
3601 tx-fifo-resize;
3603 dma-coherent;
3606 #address-cells = <1>;
3607 #size-cells = <0>;
3626 pdc: interrupt-controller@b220000 {
3627 compatible = "qcom,sm8650-pdc", "qcom,pdc";
3630 interrupt-parent = <&intc>;
3632 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3636 #interrupt-cells = <2>;
3637 interrupt-controller;
3640 tsens0: thermal-sensor@c228000 {
3641 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
3647 interrupt-names = "uplow",
3652 #thermal-sensor-cells = <1>;
3655 tsens1: thermal-sensor@c229000 {
3656 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
3662 interrupt-names = "uplow",
3667 #thermal-sensor-cells = <1>;
3670 tsens2: thermal-sensor@c22a000 {
3671 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
3677 interrupt-names = "uplow",
3682 #thermal-sensor-cells = <1>;
3685 aoss_qmp: power-management@c300000 {
3686 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
3689 interrupt-parent = <&ipcc>;
3690 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3695 #clock-cells = <0>;
3699 compatible = "qcom,rpmh-stats";
3704 compatible = "qcom,spmi-pmic-arb";
3710 reg-names = "core",
3716 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3717 interrupt-names = "periph_irq";
3721 qcom,bus-id = <0>;
3723 interrupt-controller;
3724 #interrupt-cells = <4>;
3726 #address-cells = <2>;
3727 #size-cells = <0>;
3731 compatible = "qcom,sm8650-tlmm";
3736 gpio-controller;
3737 #gpio-cells = <2>;
3739 interrupt-controller;
3740 #interrupt-cells = <2>;
3742 gpio-ranges = <&tlmm 0 0 211>;
3744 wakeup-parent = <&pdc>;
3746 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3750 drive-strength = <2>;
3751 bias-pull-up;
3754 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3758 drive-strength = <2>;
3759 bias-pull-up;
3762 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3766 drive-strength = <2>;
3767 bias-pull-up;
3770 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3774 drive-strength = <2>;
3775 bias-pull-up;
3778 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3782 drive-strength = <2>;
3783 bias-pull-up;
3786 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3790 drive-strength = <2>;
3791 bias-pull-up;
3794 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3798 drive-strength = <2>;
3799 bias-pull-up;
3802 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3806 drive-strength = <2>;
3807 bias-pull-up;
3810 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3814 drive-strength = <2>;
3815 bias-pull-up;
3818 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3822 drive-strength = <2>;
3823 bias-pull-up;
3826 pcie0_default_state: pcie0-default-state {
3827 perst-pins {
3830 drive-strength = <2>;
3831 bias-pull-down;
3834 clkreq-pins {
3837 drive-strength = <2>;
3838 bias-pull-up;
3841 wake-pins {
3844 drive-strength = <2>;
3845 bias-pull-up;
3849 pcie1_default_state: pcie1-default-state {
3850 perst-pins {
3853 drive-strength = <2>;
3854 bias-pull-down;
3857 clkreq-pins {
3860 drive-strength = <2>;
3861 bias-pull-up;
3864 wake-pins {
3867 drive-strength = <2>;
3868 bias-pull-up;
3872 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3876 drive-strength = <2>;
3877 bias-pull-up;
3880 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3884 drive-strength = <2>;
3885 bias-pull-up;
3888 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3892 drive-strength = <2>;
3893 bias-pull-up;
3896 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3900 drive-strength = <2>;
3901 bias-pull-up;
3904 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3908 drive-strength = <2>;
3909 bias-pull-up;
3912 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3916 drive-strength = <2>;
3917 bias-pull-up;
3920 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3924 drive-strength = <2>;
3925 bias-pull-up;
3928 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
3932 drive-strength = <2>;
3933 bias-pull-up;
3936 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3940 drive-strength = <2>;
3941 bias-pull-up;
3944 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3948 drive-strength = <2>;
3949 bias-pull-up;
3952 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3956 drive-strength = <2>;
3957 bias-pull-up;
3960 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3964 drive-strength = <2>;
3965 bias-pull-up;
3968 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3972 drive-strength = <2>;
3973 bias-pull-up;
3976 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3980 drive-strength = <2>;
3981 bias-pull-up;
3984 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3988 drive-strength = <2>;
3989 bias-pull-up;
3992 qup_spi0_cs: qup-spi0-cs-state {
3995 drive-strength = <6>;
3996 bias-disable;
3999 qup_spi0_data_clk: qup-spi0-data-clk-state {
4003 drive-strength = <6>;
4004 bias-disable;
4007 qup_spi1_cs: qup-spi1-cs-state {
4010 drive-strength = <6>;
4011 bias-disable;
4014 qup_spi1_data_clk: qup-spi1-data-clk-state {
4018 drive-strength = <6>;
4019 bias-disable;
4022 qup_spi2_cs: qup-spi2-cs-state {
4025 drive-strength = <6>;
4026 bias-disable;
4029 qup_spi2_data_clk: qup-spi2-data-clk-state {
4033 drive-strength = <6>;
4034 bias-disable;
4037 qup_spi3_cs: qup-spi3-cs-state {
4040 drive-strength = <6>;
4041 bias-disable;
4044 qup_spi3_data_clk: qup-spi3-data-clk-state {
4048 drive-strength = <6>;
4049 bias-disable;
4052 qup_spi4_cs: qup-spi4-cs-state {
4055 drive-strength = <6>;
4056 bias-disable;
4059 qup_spi4_data_clk: qup-spi4-data-clk-state {
4063 drive-strength = <6>;
4064 bias-disable;
4067 qup_spi5_cs: qup-spi5-cs-state {
4070 drive-strength = <6>;
4071 bias-disable;
4074 qup_spi5_data_clk: qup-spi5-data-clk-state {
4078 drive-strength = <6>;
4079 bias-disable;
4082 qup_spi6_cs: qup-spi6-cs-state {
4085 drive-strength = <6>;
4086 bias-disable;
4089 qup_spi6_data_clk: qup-spi6-data-clk-state {
4093 drive-strength = <6>;
4094 bias-disable;
4097 qup_spi7_cs: qup-spi7-cs-state {
4100 drive-strength = <6>;
4101 bias-disable;
4104 qup_spi7_data_clk: qup-spi7-data-clk-state {
4108 drive-strength = <6>;
4109 bias-disable;
4112 qup_spi8_cs: qup-spi8-cs-state {
4115 drive-strength = <6>;
4116 bias-disable;
4119 qup_spi8_data_clk: qup-spi8-data-clk-state {
4123 drive-strength = <6>;
4124 bias-disable;
4127 qup_spi9_cs: qup-spi9-cs-state {
4130 drive-strength = <6>;
4131 bias-disable;
4134 qup_spi9_data_clk: qup-spi9-data-clk-state {
4138 drive-strength = <6>;
4139 bias-disable;
4142 qup_spi10_cs: qup-spi10-cs-state {
4145 drive-strength = <6>;
4146 bias-disable;
4149 qup_spi10_data_clk: qup-spi10-data-clk-state {
4153 drive-strength = <6>;
4154 bias-disable;
4157 qup_spi11_cs: qup-spi11-cs-state {
4160 drive-strength = <6>;
4161 bias-disable;
4164 qup_spi11_data_clk: qup-spi11-data-clk-state {
4168 drive-strength = <6>;
4169 bias-disable;
4172 qup_spi12_cs: qup-spi12-cs-state {
4175 drive-strength = <6>;
4176 bias-disable;
4179 qup_spi12_data_clk: qup-spi12-data-clk-state {
4183 drive-strength = <6>;
4184 bias-disable;
4187 qup_spi13_cs: qup-spi13-cs-state {
4190 drive-strength = <6>;
4191 bias-disable;
4194 qup_spi13_data_clk: qup-spi13-data-clk-state {
4198 drive-strength = <6>;
4199 bias-disable;
4202 qup_spi14_cs: qup-spi14-cs-state {
4205 drive-strength = <6>;
4206 bias-disable;
4209 qup_spi14_data_clk: qup-spi14-data-clk-state {
4213 drive-strength = <6>;
4214 bias-disable;
4217 qup_uart14_default: qup-uart14-default-state {
4221 drive-strength = <2>;
4222 bias-pull-up;
4225 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4229 drive-strength = <2>;
4230 bias-pull-down;
4233 qup_uart15_default: qup-uart15-default-state {
4237 drive-strength = <2>;
4238 bias-disable;
4241 sdc2_sleep: sdc2-sleep-state {
4242 clk-pins {
4244 drive-strength = <2>;
4245 bias-disable;
4248 cmd-pins {
4250 drive-strength = <2>;
4251 bias-pull-up;
4254 data-pins {
4256 drive-strength = <2>;
4257 bias-pull-up;
4261 sdc2_default: sdc2-default-state {
4262 clk-pins {
4264 drive-strength = <16>;
4265 bias-disable;
4268 cmd-pins {
4270 drive-strength = <10>;
4271 bias-pull-up;
4274 data-pins {
4276 drive-strength = <10>;
4277 bias-pull-up;
4283 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4384 #iommu-cells = <2>;
4385 #global-interrupts = <1>;
4387 dma-coherent;
4390 intc: interrupt-controller@17100000 {
4391 compatible = "arm,gic-v3";
4397 #interrupt-cells = <3>;
4398 interrupt-controller;
4400 #redistributor-regions = <1>;
4401 redistributor-stride = <0 0x40000>;
4403 #address-cells = <2>;
4404 #size-cells = <2>;
4407 gic_its: msi-controller@17140000 {
4408 compatible = "arm,gic-v3-its";
4411 msi-controller;
4412 #msi-cells = <1>;
4417 compatible = "arm,armv7-timer-mem";
4421 #address-cells = <1>;
4422 #size-cells = <1>;
4431 frame-number = <0>;
4439 frame-number = <1>;
4449 frame-number = <2>;
4459 frame-number = <3>;
4469 frame-number = <4>;
4479 frame-number = <5>;
4489 frame-number = <6>;
4496 compatible = "qcom,rpmh-rsc";
4501 reg-names = "drv-0",
4502 "drv-1",
4503 "drv-2";
4509 power-domains = <&CLUSTER_PD>;
4511 qcom,tcs-offset = <0xd00>;
4512 qcom,drv-id = <2>;
4513 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4518 apps_bcm_voter: bcm-voter {
4519 compatible = "qcom,bcm-voter";
4522 rpmhcc: clock-controller {
4523 compatible = "qcom,sm8650-rpmh-clk";
4526 clock-names = "xo";
4528 #clock-cells = <1>;
4531 rpmhpd: power-controller {
4532 compatible = "qcom,sm8650-rpmhpd";
4534 operating-points-v2 = <&rpmhpd_opp_table>;
4536 #power-domain-cells = <1>;
4538 rpmhpd_opp_table: opp-table {
4539 compatible = "operating-points-v2";
4541 rpmhpd_opp_ret: opp-16 {
4542 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4545 rpmhpd_opp_min_svs: opp-48 {
4546 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4549 rpmhpd_opp_low_svs_d2: opp-52 {
4550 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4553 rpmhpd_opp_low_svs_d1: opp-56 {
4554 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4557 rpmhpd_opp_low_svs_d0: opp-60 {
4558 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4561 rpmhpd_opp_low_svs: opp-64 {
4562 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4565 rpmhpd_opp_low_svs_l1: opp-80 {
4566 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4569 rpmhpd_opp_svs: opp-128 {
4570 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4573 rpmhpd_opp_svs_l0: opp-144 {
4574 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4577 rpmhpd_opp_svs_l1: opp-192 {
4578 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4581 rpmhpd_opp_nom: opp-256 {
4582 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4585 rpmhpd_opp_nom_l1: opp-320 {
4586 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4589 rpmhpd_opp_nom_l2: opp-336 {
4590 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4593 rpmhpd_opp_turbo: opp-384 {
4594 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4597 rpmhpd_opp_turbo_l1: opp-416 {
4598 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4605 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
4610 reg-names = "freq-domain0",
4611 "freq-domain1",
4612 "freq-domain2",
4613 "freq-domain3";
4619 interrupt-names = "dcvsh-irq-0",
4620 "dcvsh-irq-1",
4621 "dcvsh-irq-2",
4622 "dcvsh-irq-3";
4625 clock-names = "xo", "alternate";
4627 #freq-domain-cells = <1>;
4628 #clock-cells = <1>;
4632 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4640 operating-points-v2 = <&llcc_bwmon_opp_table>;
4642 llcc_bwmon_opp_table: opp-table {
4643 compatible = "operating-points-v2";
4645 opp-0 {
4646 opp-peak-kBps = <2086000>;
4649 opp-1 {
4650 opp-peak-kBps = <2929000>;
4653 opp-2 {
4654 opp-peak-kBps = <5931000>;
4657 opp-3 {
4658 opp-peak-kBps = <6515000>;
4661 opp-4 {
4662 opp-peak-kBps = <7980000>;
4665 opp-5 {
4666 opp-peak-kBps = <10437000>;
4669 opp-6 {
4670 opp-peak-kBps = <12157000>;
4673 opp-7 {
4674 opp-peak-kBps = <14060000>;
4677 opp-8 {
4678 opp-peak-kBps = <16113000>;
4684 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
4692 operating-points-v2 = <&cpu_bwmon_opp_table>;
4694 cpu_bwmon_opp_table: opp-table {
4695 compatible = "operating-points-v2";
4697 opp-0 {
4698 opp-peak-kBps = <4577000>;
4701 opp-1 {
4702 opp-peak-kBps = <7110000>;
4705 opp-2 {
4706 opp-peak-kBps = <9155000>;
4709 opp-3 {
4710 opp-peak-kBps = <12298000>;
4713 opp-4 {
4714 opp-peak-kBps = <14236000>;
4717 opp-5 {
4718 opp-peak-kBps = <16265000>;
4724 compatible = "qcom,sm8650-gem-noc";
4727 qcom,bcm-voters = <&apps_bcm_voter>;
4729 #interconnect-cells = <2>;
4732 system-cache-controller@25000000 {
4733 compatible = "qcom,sm8650-llcc";
4739 reg-names = "llcc0_base",
4749 compatible = "qcom,sm8650-adsp-pas";
4752 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4757 interrupt-names = "wdog",
4761 "stop-ack";
4764 clock-names = "xo";
4769 power-domains = <&rpmhpd RPMHPD_LCX>,
4771 power-domain-names = "lcx",
4774 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4778 qcom,smem-states = <&smp2p_adsp_out 0>;
4779 qcom,smem-state-names = "stop";
4783 remoteproc_adsp_glink: glink-edge {
4784 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4791 qcom,remote-pid = <2>;
4798 qcom,glink-channels = "fastrpcglink-apps-dsp";
4802 #address-cells = <1>;
4803 #size-cells = <0>;
4805 compute-cb@3 {
4806 compatible = "qcom,fastrpc-compute-cb";
4813 compute-cb@4 {
4814 compatible = "qcom,fastrpc-compute-cb";
4821 compute-cb@5 {
4822 compatible = "qcom,fastrpc-compute-cb";
4829 compute-cb@6 {
4830 compatible = "qcom,fastrpc-compute-cb";
4837 compute-cb@7 {
4838 compatible = "qcom,fastrpc-compute-cb";
4849 qcom,glink-channels = "adsp_apps";
4852 #address-cells = <1>;
4853 #size-cells = <0>;
4858 #sound-dai-cells = <0>;
4859 qcom,protection-domain = "avs/audio",
4863 compatible = "qcom,q6apm-lpass-dais";
4864 #sound-dai-cells = <1>;
4868 compatible = "qcom,q6apm-dais";
4877 qcom,protection-domain = "avs/audio",
4880 q6prmcc: clock-controller {
4881 compatible = "qcom,q6prm-lpass-clocks";
4882 #clock-cells = <2>;
4890 compatible = "qcom,sm8650-nsp-noc";
4893 qcom,bcm-voters = <&apps_bcm_voter>;
4895 #interconnect-cells = <2>;
4899 compatible = "qcom,sm8650-cdsp-pas";
4902 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4907 interrupt-names = "wdog",
4911 "stop-ack";
4914 clock-names = "xo";
4919 power-domains = <&rpmhpd RPMHPD_CX>,
4922 power-domain-names = "cx",
4926 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
4930 qcom,smem-states = <&smp2p_cdsp_out 0>;
4931 qcom,smem-state-names = "stop";
4935 glink-edge {
4936 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4943 qcom,remote-pid = <5>;
4950 qcom,glink-channels = "fastrpcglink-apps-dsp";
4954 #address-cells = <1>;
4955 #size-cells = <0>;
4957 compute-cb@1 {
4958 compatible = "qcom,fastrpc-compute-cb";
4966 compute-cb@2 {
4967 compatible = "qcom,fastrpc-compute-cb";
4975 compute-cb@3 {
4976 compatible = "qcom,fastrpc-compute-cb";
4984 compute-cb@4 {
4985 compatible = "qcom,fastrpc-compute-cb";
4993 compute-cb@5 {
4994 compatible = "qcom,fastrpc-compute-cb";
5002 compute-cb@6 {
5003 compatible = "qcom,fastrpc-compute-cb";
5011 compute-cb@7 {
5012 compatible = "qcom,fastrpc-compute-cb";
5020 compute-cb@8 {
5021 compatible = "qcom,fastrpc-compute-cb";
5033 thermal-zones {
5034 aoss0-thermal {
5035 polling-delay-passive = <0>;
5036 polling-delay = <0>;
5037 thermal-sensors = <&tsens0 0>;
5040 trip-point0 {
5046 aoss0-critical {
5054 cpuss0-thermal {
5055 polling-delay-passive = <0>;
5056 polling-delay = <0>;
5057 thermal-sensors = <&tsens0 1>;
5060 trip-point0 {
5066 cpuss0-critical {
5074 cpuss1-thermal {
5075 polling-delay-passive = <0>;
5076 polling-delay = <0>;
5077 thermal-sensors = <&tsens0 2>;
5080 trip-point0 {
5086 cpuss1-critical {
5094 cpuss2-thermal {
5095 polling-delay-passive = <0>;
5096 polling-delay = <0>;
5097 thermal-sensors = <&tsens0 3>;
5100 trip-point0 {
5106 cpuss2-critical {
5114 cpuss3-thermal {
5115 polling-delay-passive = <0>;
5116 polling-delay = <0>;
5117 thermal-sensors = <&tsens0 4>;
5120 trip-point0 {
5126 cpuss3-critical {
5134 cpu2-top-thermal {
5135 polling-delay-passive = <0>;
5136 polling-delay = <0>;
5137 thermal-sensors = <&tsens0 5>;
5140 trip-point0 {
5146 trip-point1 {
5152 cpu2-critical {
5160 cpu2-bottom-thermal {
5161 polling-delay-passive = <0>;
5162 polling-delay = <0>;
5163 thermal-sensors = <&tsens0 6>;
5166 trip-point0 {
5172 trip-point1 {
5178 cpu2-critical {
5186 cpu3-top-thermal {
5187 polling-delay-passive = <0>;
5188 polling-delay = <0>;
5189 thermal-sensors = <&tsens0 7>;
5192 trip-point0 {
5198 trip-point1 {
5204 cpu3-critical {
5212 cpu3-bottom-thermal {
5213 polling-delay-passive = <0>;
5214 polling-delay = <0>;
5215 thermal-sensors = <&tsens0 8>;
5218 trip-point0 {
5224 trip-point1 {
5230 cpu3-critical {
5238 cpu4-top-thermal {
5239 polling-delay-passive = <0>;
5240 polling-delay = <0>;
5241 thermal-sensors = <&tsens0 9>;
5244 trip-point0 {
5250 trip-point1 {
5256 cpu4-critical {
5264 cpu4-bottom-thermal {
5265 polling-delay-passive = <0>;
5266 polling-delay = <0>;
5267 thermal-sensors = <&tsens0 10>;
5270 trip-point0 {
5276 trip-point1 {
5282 cpu4-critical {
5290 cpu5-top-thermal {
5291 polling-delay-passive = <0>;
5292 polling-delay = <0>;
5293 thermal-sensors = <&tsens0 11>;
5296 trip-point0 {
5302 trip-point1 {
5308 cpu5-critical {
5316 cpu5-bottom-thermal {
5317 polling-delay-passive = <0>;
5318 polling-delay = <0>;
5319 thermal-sensors = <&tsens0 12>;
5322 trip-point0 {
5328 trip-point1 {
5334 cpu5-critical {
5342 cpu6-top-thermal {
5343 polling-delay-passive = <0>;
5344 polling-delay = <0>;
5345 thermal-sensors = <&tsens0 13>;
5348 trip-point0 {
5354 trip-point1 {
5360 cpu6-critical {
5368 cpu6-bottom-thermal {
5369 polling-delay-passive = <0>;
5370 polling-delay = <0>;
5371 thermal-sensors = <&tsens0 14>;
5374 trip-point0 {
5380 trip-point1 {
5386 cpu6-critical {
5394 aoss1-thermal {
5395 polling-delay-passive = <0>;
5396 polling-delay = <0>;
5397 thermal-sensors = <&tsens1 0>;
5400 trip-point0 {
5406 aoss1-critical {
5414 cpu7-top-thermal {
5415 polling-delay-passive = <0>;
5416 polling-delay = <0>;
5417 thermal-sensors = <&tsens1 1>;
5420 trip-point0 {
5426 trip-point1 {
5432 cpu7-critical {
5440 cpu7-middle-thermal {
5441 polling-delay-passive = <0>;
5442 polling-delay = <0>;
5443 thermal-sensors = <&tsens1 2>;
5446 trip-point0 {
5452 trip-point1 {
5458 cpu7-critical {
5466 cpu7-bottom-thermal {
5467 polling-delay-passive = <0>;
5468 polling-delay = <0>;
5469 thermal-sensors = <&tsens1 3>;
5472 trip-point0 {
5478 trip-point1 {
5484 cpu7-critical {
5492 cpu0-thermal {
5493 polling-delay-passive = <0>;
5494 polling-delay = <0>;
5495 thermal-sensors = <&tsens1 4>;
5498 trip-point0 {
5504 trip-point1 {
5510 cpu0-critical {
5518 cpu1-thermal {
5519 polling-delay-passive = <0>;
5520 polling-delay = <0>;
5521 thermal-sensors = <&tsens1 5>;
5524 trip-point0 {
5530 trip-point1 {
5536 cpu1-critical {
5544 nsphvx0-thermal {
5545 polling-delay-passive = <10>;
5546 polling-delay = <0>;
5547 thermal-sensors = <&tsens2 6>;
5550 trip-point0 {
5556 nsphvx1-critical {
5564 nsphvx1-thermal {
5565 polling-delay-passive = <10>;
5566 polling-delay = <0>;
5567 thermal-sensors = <&tsens2 7>;
5570 trip-point0 {
5576 nsphvx1-critical {
5584 nsphmx0-thermal {
5585 polling-delay-passive = <10>;
5586 polling-delay = <0>;
5587 thermal-sensors = <&tsens2 8>;
5590 trip-point0 {
5596 nsphmx0-critical {
5604 nsphmx1-thermal {
5605 polling-delay-passive = <10>;
5606 polling-delay = <0>;
5607 thermal-sensors = <&tsens2 9>;
5610 trip-point0 {
5616 nsphmx1-critical {
5624 nsphmx2-thermal {
5625 polling-delay-passive = <10>;
5626 polling-delay = <0>;
5627 thermal-sensors = <&tsens2 10>;
5630 trip-point0 {
5636 nsphmx2-critical {
5644 nsphmx3-thermal {
5645 polling-delay-passive = <10>;
5646 polling-delay = <0>;
5647 thermal-sensors = <&tsens2 11>;
5650 trip-point0 {
5656 nsphmx3-critical {
5664 video-thermal {
5665 polling-delay-passive = <10>;
5666 polling-delay = <0>;
5667 thermal-sensors = <&tsens1 12>;
5670 trip-point0 {
5676 video-critical {
5684 ddr-thermal {
5685 polling-delay-passive = <10>;
5686 polling-delay = <0>;
5687 thermal-sensors = <&tsens1 13>;
5690 trip-point0 {
5696 ddr-critical {
5704 camera0-thermal {
5705 polling-delay-passive = <0>;
5706 polling-delay = <0>;
5707 thermal-sensors = <&tsens1 14>;
5710 trip-point0 {
5716 camera0-critical {
5724 camera1-thermal {
5725 polling-delay-passive = <0>;
5726 polling-delay = <0>;
5727 thermal-sensors = <&tsens1 15>;
5730 trip-point0 {
5736 camera1-critical {
5744 aoss2-thermal {
5745 polling-delay-passive = <0>;
5746 polling-delay = <0>;
5747 thermal-sensors = <&tsens2 0>;
5750 trip-point0 {
5756 aoss2-critical {
5764 gpuss0-thermal {
5765 polling-delay-passive = <10>;
5766 polling-delay = <0>;
5767 thermal-sensors = <&tsens2 1>;
5770 trip-point0 {
5776 gpuss0-critical {
5784 gpuss1-thermal {
5785 polling-delay-passive = <10>;
5786 polling-delay = <0>;
5787 thermal-sensors = <&tsens2 2>;
5790 trip-point0 {
5796 gpuss1-critical {
5804 gpuss2-thermal {
5805 polling-delay-passive = <10>;
5806 polling-delay = <0>;
5807 thermal-sensors = <&tsens2 3>;
5810 trip-point0 {
5816 gpuss2-critical {
5824 gpuss3-thermal {
5825 polling-delay-passive = <10>;
5826 polling-delay = <0>;
5827 thermal-sensors = <&tsens2 4>;
5830 trip-point0 {
5836 gpuss3-critical {
5844 gpuss4-thermal {
5845 polling-delay-passive = <10>;
5846 polling-delay = <0>;
5847 thermal-sensors = <&tsens2 5>;
5850 trip-point0 {
5856 gpuss4-critical {
5864 gpuss5-thermal {
5865 polling-delay-passive = <10>;
5866 polling-delay = <0>;
5867 thermal-sensors = <&tsens2 6>;
5870 trip-point0 {
5876 gpuss5-critical {
5884 gpuss6-thermal {
5885 polling-delay-passive = <10>;
5886 polling-delay = <0>;
5887 thermal-sensors = <&tsens2 7>;
5890 trip-point0 {
5896 gpuss6-critical {
5904 gpuss7-thermal {
5905 polling-delay-passive = <10>;
5906 polling-delay = <0>;
5907 thermal-sensors = <&tsens2 8>;
5910 trip-point0 {
5916 gpuss7-critical {
5924 modem0-thermal {
5925 polling-delay-passive = <0>;
5926 polling-delay = <0>;
5927 thermal-sensors = <&tsens2 9>;
5930 trip-point0 {
5936 modem0-critical {
5944 modem1-thermal {
5945 polling-delay-passive = <0>;
5946 polling-delay = <0>;
5947 thermal-sensors = <&tsens2 10>;
5950 trip-point0 {
5956 modem1-critical {
5964 modem2-thermal {
5965 polling-delay-passive = <0>;
5966 polling-delay = <0>;
5967 thermal-sensors = <&tsens2 11>;
5970 trip-point0 {
5976 modem2-critical {
5984 modem3-thermal {
5985 polling-delay-passive = <0>;
5986 polling-delay = <0>;
5987 thermal-sensors = <&tsens2 12>;
5990 trip-point0 {
5996 modem3-critical {
6006 compatible = "arm,armv8-timer";