dts/qcom/sm4450.dtsi

1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 	interrupt-parent = <&intc>;
15 	#address-cells = <2>;
16 	#size-cells = <2>;
21 		xo_board: xo-board {
22 			compatible = "fixed-clock";
23 			clock-frequency = <76800000>;
24 			#clock-cells = <0>;
27 		sleep_clk: sleep-clk {
28 			compatible = "fixed-clock";
29 			clock-frequency = <32000>;
30 			#clock-cells = <0>;
35 		#address-cells = <2>;
36 		#size-cells = <0>;
40 			compatible = "arm,cortex-a55";
42 			enable-method = "psci";
43 			next-level-cache = <&L2_0>;
44 			power-domains = <&CPU_PD0>;
45 			power-domain-names = "psci";
46 			#cooling-cells = <2>;
48 			L2_0: l2-cache {
50 				cache-level = <2>;
51 				cache-unified;
52 				next-level-cache = <&L3_0>;
54 				L3_0: l3-cache {
56 					cache-level = <3>;
57 					cache-unified;
64 			compatible = "arm,cortex-a55";
66 			enable-method = "psci";
67 			next-level-cache = <&L2_100>;
68 			power-domains = <&CPU_PD0>;
69 			power-domain-names = "psci";
70 			#cooling-cells = <2>;
72 			L2_100: l2-cache {
74 				cache-level = <2>;
75 				cache-unified;
76 				next-level-cache = <&L3_0>;
82 			compatible = "arm,cortex-a55";
84 			enable-method = "psci";
85 			next-level-cache = <&L2_200>;
86 			power-domains = <&CPU_PD0>;
87 			power-domain-names = "psci";
88 			#cooling-cells = <2>;
90 			L2_200: l2-cache {
92 				cache-level = <2>;
93 				cache-unified;
94 				next-level-cache = <&L3_0>;
100 			compatible = "arm,cortex-a55";
102 			enable-method = "psci";
103 			next-level-cache = <&L2_300>;
104 			power-domains = <&CPU_PD0>;
105 			power-domain-names = "psci";
106 			#cooling-cells = <2>;
108 			L2_300: l2-cache {
110 				cache-level = <2>;
111 				cache-unified;
112 				next-level-cache = <&L3_0>;
118 			compatible = "arm,cortex-a55";
120 			enable-method = "psci";
121 			next-level-cache = <&L2_400>;
122 			power-domains = <&CPU_PD0>;
123 			power-domain-names = "psci";
124 			#cooling-cells = <2>;
126 			L2_400: l2-cache {
128 				cache-level = <2>;
129 				cache-unified;
130 				next-level-cache = <&L3_0>;
136 			compatible = "arm,cortex-a55";
138 			enable-method = "psci";
139 			next-level-cache = <&L2_500>;
140 			power-domains = <&CPU_PD0>;
141 			power-domain-names = "psci";
142 			#cooling-cells = <2>;
144 			L2_500: l2-cache {
146 				cache-level = <2>;
147 				cache-unified;
148 				next-level-cache = <&L3_0>;
154 			compatible = "arm,cortex-a78";
156 			enable-method = "psci";
157 			next-level-cache = <&L2_600>;
158 			power-domains = <&CPU_PD0>;
159 			power-domain-names = "psci";
160 			#cooling-cells = <2>;
162 			L2_600: l2-cache {
164 				cache-level = <2>;
165 				cache-unified;
166 				next-level-cache = <&L3_0>;
172 			compatible = "arm,cortex-a78";
174 			enable-method = "psci";
175 			next-level-cache = <&L2_700>;
176 			power-domains = <&CPU_PD0>;
177 			power-domain-names = "psci";
178 			#cooling-cells = <2>;
180 			L2_700: l2-cache {
182 				cache-level = <2>;
183 				cache-unified;
184 				next-level-cache = <&L3_0>;
188 		cpu-map {
224 		idle-states {
225 			entry-method = "psci";
227 			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
228 				compatible = "arm,idle-state";
229 				arm,psci-suspend-param = <0x40000004>;
230 				entry-latency-us = <800>;
231 				exit-latency-us = <750>;
232 				min-residency-us = <4090>;
233 				local-timer-stop;
236 			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
237 				compatible = "arm,idle-state";
238 				arm,psci-suspend-param = <0x40000004>;
239 				entry-latency-us = <600>;
240 				exit-latency-us = <1550>;
241 				min-residency-us = <4791>;
242 				local-timer-stop;
246 		domain-idle-states {
247 			CLUSTER_SLEEP_0: cluster-sleep-0 {
248 				compatible = "domain-idle-state";
249 				arm,psci-suspend-param = <0x41000044>;
250 				entry-latency-us = <1050>;
251 				exit-latency-us = <2500>;
252 				min-residency-us = <5309>;
255 			CLUSTER_SLEEP_1: cluster-sleep-1 {
256 				compatible = "domain-idle-state";
257 				arm,psci-suspend-param = <0x41003344>;
258 				entry-latency-us = <1561>;
259 				exit-latency-us = <2801>;
260 				min-residency-us = <8550>;
272 		compatible = "arm,armv8-pmuv3";
277 		compatible = "arm,psci-1.0";
280 		CPU_PD0: power-domain-cpu0 {
281 			#power-domain-cells = <0>;
282 			power-domains = <&CLUSTER_PD>;
283 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
286 		CPU_PD1: power-domain-cpu1 {
287 			#power-domain-cells = <0>;
288 			power-domains = <&CLUSTER_PD>;
289 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
292 		CPU_PD2: power-domain-cpu2 {
293 			#power-domain-cells = <0>;
294 			power-domains = <&CLUSTER_PD>;
295 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
298 		CPU_PD3: power-domain-cpu3 {
299 			#power-domain-cells = <0>;
300 			power-domains = <&CLUSTER_PD>;
301 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
304 		CPU_PD4: power-domain-cpu4 {
305 			#power-domain-cells = <0>;
306 			power-domains = <&CLUSTER_PD>;
307 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
310 		CPU_PD5: power-domain-cpu5 {
311 			#power-domain-cells = <0>;
312 			power-domains = <&CLUSTER_PD>;
313 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
316 		CPU_PD6: power-domain-cpu6 {
317 			#power-domain-cells = <0>;
318 			power-domains = <&CLUSTER_PD>;
319 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
322 		CPU_PD7: power-domain-cpu7 {
323 			#power-domain-cells = <0>;
324 			power-domains = <&CLUSTER_PD>;
325 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
328 		CLUSTER_PD: power-domain-cpu-cluster0 {
329 			#power-domain-cells = <0>;
330 			domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
334 	reserved_memory: reserved-memory {
335 		#address-cells = <2>;
336 		#size-cells = <2>;
339 		aop_cmd_db_mem: cmd-db@80860000 {
340 			compatible = "qcom,cmd-db";
342 			no-map;
347 		#address-cells = <2>;
348 		#size-cells = <2>;
350 		dma-ranges = <0 0 0 0 0x10 0>;
351 		compatible = "simple-bus";
353 		gcc: clock-controller@100000 {
354 			compatible = "qcom,sm4450-gcc";
356 			#clock-cells = <1>;
357 			#reset-cells = <1>;
358 			#power-domain-cells = <1>;
368 			compatible = "qcom,geni-se-qup";
373 			clock-names = "m-ahb", "s-ahb";
374 			#address-cells = <2>;
375 			#size-cells = <2>;
379 				compatible = "qcom,geni-debug-uart";
382 				clock-names = "se";
384 				pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
385 				pinctrl-names = "default";
391 			compatible = "qcom,tcsr-mutex";
393 			#hwlock-cells = <1>;
396 		pdc: interrupt-controller@b220000 {
397 			compatible = "qcom,sm4450-pdc", "qcom,pdc";
399 			qcom,pdc-ranges = <0 480 94>, <94 494 31>,
401 			#interrupt-cells = <2>;
402 			interrupt-parent = <&intc>;
403 			interrupt-controller;
407 			compatible = "qcom,sm4450-tlmm";
410 			gpio-controller;
411 			#gpio-cells = <2>;
412 			interrupt-controller;
413 			#interrupt-cells = <2>;
414 			gpio-ranges = <&tlmm 0 0 137>;
415 			wakeup-parent = <&pdc>;
417 			qup_uart7_rx: qup-uart7-rx-state {
420 				drive-strength = <2>;
421 				bias-disable;
424 			qup_uart7_tx: qup-uart7-tx-state {
427 				drive-strength = <2>;
428 				bias-disable;
432 		intc: interrupt-controller@17200000 {
433 			compatible = "arm,gic-v3";
437 			#interrupt-cells = <3>;
438 			interrupt-controller;
439 			#redistributor-regions = <1>;
440 			redistributor-stride = <0x0 0x20000>;
444 			compatible = "arm,armv7-timer-mem";
447 			#address-cells = <1>;
448 			#size-cells = <1>;
453 				frame-number = <0>;
460 				frame-number = <1>;
467 				frame-number = <2>;
474 				frame-number = <3>;
481 				frame-number = <4>;
488 				frame-number = <5>;
495 				frame-number = <6>;
502 			compatible = "qcom,rpmh-rsc";
506 			reg-names = "drv-0", "drv-1", "drv-2";
511 			qcom,tcs-offset = <0xd00>;
512 			qcom,drv-id = <2>;
513 			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
515 			power-domains = <&CLUSTER_PD>;
517 			apps_bcm_voter: bcm-voter {
518 				compatible = "qcom,bcm-voter";
521 			rpmhcc: clock-controller {
522 				compatible = "qcom,sm4450-rpmh-clk";
523 				#clock-cells = <1>;
525 				clock-names = "xo";
532 		compatible = "arm,armv8-timer";