Lines Matching +full:gcc +full:- +full:ipq8074
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <19200000>;
27 #clock-cells = <0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a53";
39 next-level-cache = <&L2_0>;
40 enable-method = "psci";
45 compatible = "arm,cortex-a53";
46 enable-method = "psci";
48 next-level-cache = <&L2_0>;
53 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 next-level-cache = <&L2_0>;
61 compatible = "arm,cortex-a53";
62 enable-method = "psci";
64 next-level-cache = <&L2_0>;
67 L2_0: l2-cache {
69 cache-level = <2>;
70 cache-unified;
75 compatible = "arm,cortex-a53-pmu";
80 compatible = "arm,psci-1.0";
84 reserved-memory {
85 #address-cells = <2>;
86 #size-cells = <2>;
91 no-map;
96 no-map;
102 no-map;
109 no-map;
115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tcsr 0x6100>;
121 #address-cells = <1>;
122 #size-cells = <1>;
124 compatible = "simple-bus";
127 compatible = "qcom,ipq8074-qmp-usb3-phy";
130 clocks = <&gcc GCC_USB1_AUX_CLK>,
132 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
133 <&gcc GCC_USB1_PIPE_CLK>;
134 clock-names = "aux",
138 clock-output-names = "usb3phy_1_cc_pipe_clk";
139 #clock-cells = <0>;
140 #phy-cells = <0>;
142 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB3PHY_1_PHY_BCR>;
144 reset-names = "phy",
151 compatible = "qcom,ipq8074-qusb2-phy";
153 #phy-cells = <0>;
155 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
157 clock-names = "cfg_ahb", "ref";
159 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
164 compatible = "qcom,ipq8074-qmp-usb3-phy";
167 clocks = <&gcc GCC_USB0_AUX_CLK>,
169 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
170 <&gcc GCC_USB0_PIPE_CLK>;
171 clock-names = "aux",
175 clock-output-names = "usb3phy_0_cc_pipe_clk";
176 #clock-cells = <0>;
177 #phy-cells = <0>;
179 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 reset-names = "phy",
188 compatible = "qcom,ipq8074-qusb2-phy";
190 #phy-cells = <0>;
192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
194 clock-names = "cfg_ahb", "ref";
196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
204 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCIE0_AHB_CLK>,
206 <&gcc GCC_PCIE0_PIPE_CLK>;
207 clock-names = "aux",
211 clock-output-names = "pcie20_phy0_pipe_clk";
212 #clock-cells = <0>;
214 #phy-cells = <0>;
216 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy",
224 compatible = "qcom,ipq8074-qmp-pcie-phy";
227 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCIE1_AHB_CLK>,
229 <&gcc GCC_PCIE1_PIPE_CLK>;
230 clock-names = "aux",
234 clock-output-names = "pcie20_phy1_pipe_clk";
235 #clock-cells = <0>;
237 #phy-cells = <0>;
239 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy",
247 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
249 #address-cells = <1>;
250 #size-cells = <0>;
252 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdio_ahb_clk";
259 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
261 #address-cells = <1>;
262 #size-cells = <1>;
266 compatible = "qcom,prng-ee";
268 clocks = <&gcc GCC_PRNG_AHB_CLK>;
269 clock-names = "core";
273 tsens: thermal-sensor@4a9000 {
274 compatible = "qcom,ipq8074-tsens";
278 interrupt-names = "combined";
280 #thermal-sensor-cells = <1>;
283 cryptobam: dma-controller@704000 {
284 compatible = "qcom,bam-v1.7.0";
287 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
288 clock-names = "bam_clk";
289 #dma-cells = <1>;
291 qcom,controlled-remotely;
296 compatible = "qcom,crypto-v5.1";
298 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
299 <&gcc GCC_CRYPTO_AXI_CLK>,
300 <&gcc GCC_CRYPTO_CLK>;
301 clock-names = "iface", "bus", "core";
303 dma-names = "rx", "tx";
308 compatible = "qcom,ipq8074-pinctrl";
311 gpio-controller;
312 gpio-ranges = <&tlmm 0 0 70>;
313 #gpio-cells = <2>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
317 serial_4_pins: serial4-state {
320 drive-strength = <8>;
321 bias-disable;
324 i2c_0_pins: i2c-0-state {
327 drive-strength = <8>;
328 bias-disable;
331 spi_0_pins: spi-0-state {
334 drive-strength = <8>;
335 bias-disable;
338 hsuart_pins: hsuart-state {
341 drive-strength = <8>;
342 bias-disable;
345 qpic_pins: qpic-state {
352 drive-strength = <8>;
353 bias-disable;
357 gcc: gcc@1800000 { label
358 compatible = "qcom,gcc-ipq8074";
364 clock-names = "xo",
368 #clock-cells = <1>;
369 #power-domain-cells = <1>;
370 #reset-cells = <1>;
374 compatible = "qcom,tcsr-mutex";
376 #hwlock-cells = <1>;
380 compatible = "qcom,tcsr-ipq8074", "syscon";
385 compatible = "qcom,spmi-pmic-arb";
391 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
393 interrupt-names = "periph_irq";
396 #address-cells = <2>;
397 #size-cells = <0>;
398 interrupt-controller;
399 #interrupt-cells = <4>;
403 compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
405 reg-names = "hc", "core";
409 interrupt-names = "hc_irq", "pwr_irq";
411 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
412 <&gcc GCC_SDCC1_APPS_CLK>,
414 clock-names = "iface", "core", "xo";
415 resets = <&gcc GCC_SDCC1_BCR>;
416 max-frequency = <384000000>;
417 mmc-ddr-1_8v;
418 mmc-hs200-1_8v;
419 mmc-hs400-1_8v;
420 bus-width = <8>;
425 blsp_dma: dma-controller@7884000 {
426 compatible = "qcom,bam-v1.7.0";
429 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
430 clock-names = "bam_clk";
431 #dma-cells = <1>;
436 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
439 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
440 <&gcc GCC_BLSP1_AHB_CLK>;
441 clock-names = "core", "iface";
446 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
449 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
450 <&gcc GCC_BLSP1_AHB_CLK>;
451 clock-names = "core", "iface";
454 dma-names = "tx", "rx";
455 pinctrl-0 = <&hsuart_pins>;
456 pinctrl-names = "default";
461 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
464 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
465 <&gcc GCC_BLSP1_AHB_CLK>;
466 clock-names = "core", "iface";
467 pinctrl-0 = <&serial_4_pins>;
468 pinctrl-names = "default";
473 compatible = "qcom,spi-qup-v2.2.1";
474 #address-cells = <1>;
475 #size-cells = <0>;
478 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
479 <&gcc GCC_BLSP1_AHB_CLK>;
480 clock-names = "core", "iface";
482 dma-names = "tx", "rx";
483 pinctrl-0 = <&spi_0_pins>;
484 pinctrl-names = "default";
489 compatible = "qcom,i2c-qup-v2.2.1";
490 #address-cells = <1>;
491 #size-cells = <0>;
494 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
495 <&gcc GCC_BLSP1_AHB_CLK>;
496 clock-names = "core", "iface";
497 clock-frequency = <400000>;
499 dma-names = "tx", "rx";
500 pinctrl-0 = <&i2c_0_pins>;
501 pinctrl-names = "default";
506 compatible = "qcom,i2c-qup-v2.2.1";
507 #address-cells = <1>;
508 #size-cells = <0>;
511 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
512 <&gcc GCC_BLSP1_AHB_CLK>;
513 clock-names = "core", "iface";
514 clock-frequency = <100000>;
516 dma-names = "tx", "rx";
521 compatible = "qcom,spi-qup-v2.2.1";
522 #address-cells = <1>;
523 #size-cells = <0>;
526 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
527 <&gcc GCC_BLSP1_AHB_CLK>;
528 clock-names = "core", "iface";
530 dma-names = "tx", "rx";
535 compatible = "qcom,i2c-qup-v2.2.1";
536 #address-cells = <1>;
537 #size-cells = <0>;
540 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
541 <&gcc GCC_BLSP1_AHB_CLK>;
542 clock-names = "core", "iface";
543 clock-frequency = <400000>;
545 dma-names = "tx", "rx";
550 compatible = "qcom,spi-qup-v2.2.1";
551 #address-cells = <1>;
552 #size-cells = <0>;
555 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
556 <&gcc GCC_BLSP1_AHB_CLK>;
557 clock-names = "core", "iface";
559 dma-names = "tx", "rx";
564 compatible = "qcom,i2c-qup-v2.2.1";
565 #address-cells = <1>;
566 #size-cells = <0>;
569 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
570 <&gcc GCC_BLSP1_AHB_CLK>;
571 clock-names = "core", "iface";
572 clock-frequency = <100000>;
574 dma-names = "tx", "rx";
578 qpic_bam: dma-controller@7984000 {
579 compatible = "qcom,bam-v1.7.0";
582 clocks = <&gcc GCC_QPIC_AHB_CLK>;
583 clock-names = "bam_clk";
584 #dma-cells = <1>;
589 qpic_nand: nand-controller@79b0000 {
590 compatible = "qcom,ipq8074-nand";
592 #address-cells = <1>;
593 #size-cells = <0>;
594 clocks = <&gcc GCC_QPIC_CLK>,
595 <&gcc GCC_QPIC_AHB_CLK>;
596 clock-names = "core", "aon";
601 dma-names = "tx", "rx", "cmd";
602 pinctrl-0 = <&qpic_pins>;
603 pinctrl-names = "default";
608 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
610 #address-cells = <1>;
611 #size-cells = <1>;
614 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
615 <&gcc GCC_USB0_MASTER_CLK>,
616 <&gcc GCC_USB0_SLEEP_CLK>,
617 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
618 clock-names = "cfg_noc",
623 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
624 <&gcc GCC_USB0_MASTER_CLK>,
625 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
626 assigned-clock-rates = <133330000>,
630 power-domains = <&gcc USB0_GDSC>;
632 resets = <&gcc GCC_USB0_BCR>;
640 phy-names = "usb2-phy", "usb3-phy";
641 snps,is-utmi-l1-suspend;
642 snps,hird-threshold = /bits/ 8 <0x0>;
650 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
652 #address-cells = <1>;
653 #size-cells = <1>;
656 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
657 <&gcc GCC_USB1_MASTER_CLK>,
658 <&gcc GCC_USB1_SLEEP_CLK>,
659 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
660 clock-names = "cfg_noc",
665 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
666 <&gcc GCC_USB1_MASTER_CLK>,
667 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
668 assigned-clock-rates = <133330000>,
672 power-domains = <&gcc USB1_GDSC>;
674 resets = <&gcc GCC_USB1_BCR>;
682 phy-names = "usb2-phy", "usb3-phy";
683 snps,is-utmi-l1-suspend;
684 snps,hird-threshold = /bits/ 8 <0x0>;
691 intc: interrupt-controller@b000000 {
692 compatible = "qcom,msm-qgic2";
693 #address-cells = <1>;
694 #size-cells = <1>;
695 interrupt-controller;
696 #interrupt-cells = <3>;
701 compatible = "arm,gic-v2m-frame";
702 msi-controller;
708 compatible = "qcom,kpss-wdt";
712 timeout-sec = <30>;
716 compatible = "qcom,ipq8074-apcs-apps-global",
717 "qcom,ipq6018-apcs-apps-global";
719 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
720 clock-names = "pll", "xo", "gpll0";
722 #clock-cells = <1>;
723 #mbox-cells = <1>;
727 compatible = "qcom,ipq8074-a53pll";
729 #clock-cells = <0>;
731 clock-names = "xo";
735 #address-cells = <1>;
736 #size-cells = <1>;
738 compatible = "arm,armv7-timer-mem";
742 frame-number = <0>;
750 frame-number = <1>;
757 frame-number = <2>;
764 frame-number = <3>;
771 frame-number = <4>;
778 frame-number = <5>;
785 frame-number = <6>;
793 compatible = "qcom,pcie-ipq8074";
798 reg-names = "dbi", "elbi", "parf", "config";
800 linux,pci-domain = <1>;
801 bus-range = <0x00 0xff>;
802 num-lanes = <1>;
803 max-link-speed = <2>;
804 #address-cells = <3>;
805 #size-cells = <2>;
808 phy-names = "pciephy";
814 interrupt-names = "msi";
815 #interrupt-cells = <1>;
816 interrupt-map-mask = <0 0 0 0x7>;
817 interrupt-map = <0 0 0 1 &intc 0 0 142
826 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
827 <&gcc GCC_PCIE1_AXI_M_CLK>,
828 <&gcc GCC_PCIE1_AXI_S_CLK>,
829 <&gcc GCC_PCIE1_AHB_CLK>,
830 <&gcc GCC_PCIE1_AUX_CLK>;
831 clock-names = "iface",
836 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
837 <&gcc GCC_PCIE1_SLEEP_ARES>,
838 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
839 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
840 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
841 <&gcc GCC_PCIE1_AHB_ARES>,
842 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
843 reset-names = "pipe",
854 compatible = "qcom,pcie-ipq8074-gen3";
860 reg-names = "dbi", "elbi", "atu", "parf", "config";
862 linux,pci-domain = <0>;
863 bus-range = <0x00 0xff>;
864 num-lanes = <1>;
865 max-link-speed = <3>;
866 #address-cells = <3>;
867 #size-cells = <2>;
870 phy-names = "pciephy";
876 interrupt-names = "msi";
877 #interrupt-cells = <1>;
878 interrupt-map-mask = <0 0 0 0x7>;
879 interrupt-map = <0 0 0 1 &intc 0 0 75
888 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
889 <&gcc GCC_PCIE0_AXI_M_CLK>,
890 <&gcc GCC_PCIE0_AXI_S_CLK>,
891 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
892 <&gcc GCC_PCIE0_RCHNG_CLK>;
893 clock-names = "iface",
899 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
900 <&gcc GCC_PCIE0_SLEEP_ARES>,
901 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
902 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
903 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
904 <&gcc GCC_PCIE0_AHB_ARES>,
905 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
906 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
907 reset-names = "pipe",
920 compatible = "arm,armv8-timer";
927 thermal-zones {
928 nss-top-thermal {
929 polling-delay-passive = <250>;
930 polling-delay = <1000>;
932 thermal-sensors = <&tsens 4>;
935 nss-top-crit {
943 nss0-thermal {
944 polling-delay-passive = <250>;
945 polling-delay = <1000>;
947 thermal-sensors = <&tsens 5>;
950 nss-0-crit {
958 nss1-thermal {
959 polling-delay-passive = <250>;
960 polling-delay = <1000>;
962 thermal-sensors = <&tsens 6>;
965 nss-1-crit {
973 wcss-phya0-thermal {
974 polling-delay-passive = <250>;
975 polling-delay = <1000>;
977 thermal-sensors = <&tsens 7>;
980 wcss-phya0-crit {
988 wcss-phya1-thermal {
989 polling-delay-passive = <250>;
990 polling-delay = <1000>;
992 thermal-sensors = <&tsens 8>;
995 wcss-phya1-crit {
1003 cpu0_thermal: cpu0-thermal {
1004 polling-delay-passive = <250>;
1005 polling-delay = <1000>;
1007 thermal-sensors = <&tsens 9>;
1010 cpu0-crit {
1018 cpu1_thermal: cpu1-thermal {
1019 polling-delay-passive = <250>;
1020 polling-delay = <1000>;
1022 thermal-sensors = <&tsens 10>;
1025 cpu1-crit {
1033 cpu2_thermal: cpu2-thermal {
1034 polling-delay-passive = <250>;
1035 polling-delay = <1000>;
1037 thermal-sensors = <&tsens 11>;
1040 cpu2-crit {
1048 cpu3_thermal: cpu3-thermal {
1049 polling-delay-passive = <250>;
1050 polling-delay = <1000>;
1052 thermal-sensors = <&tsens 12>;
1055 cpu3-crit {
1063 cluster_thermal: cluster-thermal {
1064 polling-delay-passive = <250>;
1065 polling-delay = <1000>;
1067 thermal-sensors = <&tsens 13>;
1070 cluster-crit {
1078 wcss-phyb0-thermal {
1079 polling-delay-passive = <250>;
1080 polling-delay = <1000>;
1082 thermal-sensors = <&tsens 14>;
1085 wcss-phyb0-crit {
1093 wcss-phyb1-thermal {
1094 polling-delay-passive = <250>;
1095 polling-delay = <1000>;
1097 thermal-sensors = <&tsens 15>;
1100 wcss-phyb1-crit {