Lines Matching +full:kpss +full:- +full:gcc
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
11 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
24 xo_board_clk: xo-board-clk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 next-level-cache = <&L2_0>;
41 operating-points-v2 = <&cpu_opp_table>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 next-level-cache = <&L2_0>;
51 operating-points-v2 = <&cpu_opp_table>;
54 L2_0: l2-cache {
56 cache-level = <2>;
57 cache-size = <0x80000>;
58 cache-unified;
62 cpu_opp_table: opp-table-cpu {
63 compatible = "operating-points-v2";
64 opp-shared;
66 opp-800000000 {
67 opp-hz = /bits/ 64 <800000000>;
68 opp-microvolt = <1100000>;
69 clock-latency-ns = <200000>;
72 opp-1008000000 {
73 opp-hz = /bits/ 64 <1008000000>;
74 opp-microvolt = <1100000>;
75 clock-latency-ns = <200000>;
81 compatible = "qcom,scm-ipq5018", "qcom,scm";
82 qcom,sdi-enabled;
93 compatible = "arm,cortex-a53-pmu";
98 compatible = "arm,psci-1.0";
102 reserved-memory {
103 #address-cells = <2>;
104 #size-cells = <2>;
109 no-map;
114 no-map;
120 no-map;
127 no-map;
132 compatible = "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
138 compatible = "qcom,ipq5018-usb-hsphy";
141 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
143 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
145 #phy-cells = <0>;
151 compatible = "qcom,ipq5018-tlmm";
154 gpio-controller;
155 #gpio-cells = <2>;
156 gpio-ranges = <&tlmm 0 0 47>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
160 uart1_pins: uart1-state {
163 drive-strength = <8>;
164 bias-pull-down;
168 gcc: clock-controller@1800000 { label
169 compatible = "qcom,gcc-ipq5018";
180 #clock-cells = <1>;
181 #reset-cells = <1>;
182 #power-domain-cells = <1>;
186 compatible = "qcom,tcsr-mutex";
188 #hwlock-cells = <1>;
192 compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
194 reg-names = "hc";
198 interrupt-names = "hc_irq", "pwr_irq";
200 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
201 <&gcc GCC_SDCC1_APPS_CLK>,
203 clock-names = "iface", "core", "xo";
204 non-removable;
208 blsp_dma: dma-controller@7884000 {
209 compatible = "qcom,bam-v1.7.0";
212 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
213 clock-names = "bam_clk";
214 #dma-cells = <1>;
219 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
222 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
223 <&gcc GCC_BLSP1_AHB_CLK>;
224 clock-names = "core", "iface";
229 compatible = "qcom,spi-qup-v2.2.1";
230 #address-cells = <1>;
231 #size-cells = <0>;
234 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
235 <&gcc GCC_BLSP1_AHB_CLK>;
236 clock-names = "core", "iface";
238 dma-names = "tx", "rx";
243 compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
247 interrupt-names = "hs_phy_irq";
249 clocks = <&gcc GCC_USB0_MASTER_CLK>,
250 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
251 <&gcc GCC_USB0_SLEEP_CLK>,
252 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
253 clock-names = "core",
258 resets = <&gcc GCC_USB0_BCR>;
260 qcom,select-utmi-as-pipe-clk;
261 #address-cells = <1>;
262 #size-cells = <1>;
270 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
271 clock-names = "ref";
273 phy-names = "usb2-phy";
275 tx-fifo-resize;
276 snps,is-utmi-l1-suspend;
277 snps,hird-threshold = /bits/ 8 <0x0>;
283 intc: interrupt-controller@b000000 {
284 compatible = "qcom,msm-qgic2";
290 interrupt-controller;
291 #interrupt-cells = <3>;
292 #address-cells = <1>;
293 #size-cells = <1>;
297 compatible = "arm,gic-v2m-frame";
299 msi-controller;
303 compatible = "arm,gic-v2m-frame";
305 msi-controller;
310 compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
317 compatible = "qcom,ipq5018-apcs-apps-global",
318 "qcom,ipq6018-apcs-apps-global";
320 #clock-cells = <1>;
321 clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
322 clock-names = "pll", "xo", "gpll0";
323 #mbox-cells = <1>;
327 compatible = "qcom,ipq5018-a53pll";
329 #clock-cells = <0>;
331 clock-names = "xo";
335 compatible = "arm,armv7-timer-mem";
337 #address-cells = <1>;
338 #size-cells = <1>;
346 frame-number = <0>;
352 frame-number = <1>;
357 frame-number = <2>;
366 frame-number = <3>;
373 frame-number = <4>;
380 frame-number = <5>;
387 frame-number = <6>;
394 compatible = "arm,armv8-timer";