dts/microchip/sparx5_pcb135_board.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 	gpio-restart {
11 		compatible = "gpio-restart";
17 		compatible = "gpio-leds";
21 			default-state = "off";
26 			default-state = "off";
31 			default-state = "off";
36 			default-state = "off";
41 			default-state = "off";
46 			default-state = "off";
51 			default-state = "off";
56 			default-state = "off";
62 	i2cmux_pins_i: i2cmux-pins {
66 		output-low;
68 	i2cmux_s29: i2cmux-0-pins {
71 		output-high;
73 	i2cmux_s30: i2cmux-1-pins {
76 		output-high;
78 	i2cmux_s31: i2cmux-2-pins {
81 		output-high;
83 	i2cmux_s32: i2cmux-3-pins {
86 		output-high;
93 		compatible = "jedec,spi-nor";
94 		spi-max-frequency = <8000000>;
102 		compatible = "spi-mux";
103 		mux-controls = <&mux>;
104 		#address-cells = <1>;
105 		#size-cells = <0>;
108 			compatible = "jedec,spi-nor";
109 			spi-max-frequency = <8000000>;
117 	microchip,sgpio-port-ranges = <24 31>;
128 	microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
132 	i2c0_imux: i2c0-imux@0 {
133 		compatible = "i2c-mux-pinctrl";
134 		#address-cells = <1>;
135 		#size-cells = <0>;
136 		i2c-parent = <&i2c0>;
141 	pinctrl-names =
144 	pinctrl-0 = <&i2cmux_s29>;
145 	pinctrl-1 = <&i2cmux_s30>;
146 	pinctrl-2 = <&i2cmux_s31>;
147 	pinctrl-3 = <&i2cmux_s32>;
148 	pinctrl-4 = <&i2cmux_pins_i>;
151 		#address-cells = <1>;
152 		#size-cells = <0>;
156 		#address-cells = <1>;
157 		#size-cells = <0>;
161 		#address-cells = <1>;
162 		#size-cells = <0>;
166 		#address-cells = <1>;
167 		#size-cells = <0>;
172 	sfp_eth60: sfp-eth60 {
174 		i2c-bus = <&i2c_sfp1>;
175 		tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
176 		rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
177 		los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
178 		mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
179 		tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
181 	sfp_eth61: sfp-eth61 {
183 		i2c-bus = <&i2c_sfp2>;
184 		tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
185 		rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
186 		los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
187 		mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
188 		tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
190 	sfp_eth62: sfp-eth62 {
192 		i2c-bus = <&i2c_sfp3>;
193 		tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
194 		rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
195 		los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
196 		mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
197 		tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
199 	sfp_eth63: sfp-eth63 {
201 		i2c-bus = <&i2c_sfp4>;
202 		tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
203 		rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
204 		los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
205 		mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
206 		tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
212 	phy0: ethernet-phy@0 {
215 	phy1: ethernet-phy@1 {
218 	phy2: ethernet-phy@2 {
221 	phy3: ethernet-phy@3 {
224 	phy4: ethernet-phy@4 {
227 	phy5: ethernet-phy@5 {
230 	phy6: ethernet-phy@6 {
233 	phy7: ethernet-phy@7 {
236 	phy8: ethernet-phy@8 {
239 	phy9: ethernet-phy@9 {
242 	phy10: ethernet-phy@10 {
245 	phy11: ethernet-phy@11 {
248 	phy12: ethernet-phy@12 {
251 	phy13: ethernet-phy@13 {
254 	phy14: ethernet-phy@14 {
257 	phy15: ethernet-phy@15 {
260 	phy16: ethernet-phy@16 {
263 	phy17: ethernet-phy@17 {
266 	phy18: ethernet-phy@18 {
269 	phy19: ethernet-phy@19 {
272 	phy20: ethernet-phy@20 {
275 	phy21: ethernet-phy@21 {
278 	phy22: ethernet-phy@22 {
281 	phy23: ethernet-phy@23 {
288 	phy24: ethernet-phy@24 {
291 	phy25: ethernet-phy@25 {
294 	phy26: ethernet-phy@26 {
297 	phy27: ethernet-phy@27 {
300 	phy28: ethernet-phy@28 {
303 	phy29: ethernet-phy@29 {
306 	phy30: ethernet-phy@30 {
309 	phy31: ethernet-phy@31 {
312 	phy32: ethernet-phy@32 {
315 	phy33: ethernet-phy@33 {
318 	phy34: ethernet-phy@34 {
321 	phy35: ethernet-phy@35 {
324 	phy36: ethernet-phy@36 {
327 	phy37: ethernet-phy@37 {
330 	phy38: ethernet-phy@38 {
333 	phy39: ethernet-phy@39 {
336 	phy40: ethernet-phy@40 {
339 	phy41: ethernet-phy@41 {
342 	phy42: ethernet-phy@42 {
345 	phy43: ethernet-phy@43 {
348 	phy44: ethernet-phy@44 {
351 	phy45: ethernet-phy@45 {
354 	phy46: ethernet-phy@46 {
357 	phy47: ethernet-phy@47 {
364 	phy64: ethernet-phy@64 {
370 	ethernet-ports {
371 		#address-cells = <1>;
372 		#size-cells = <0>;
378 			phy-handle = <&phy0>;
379 			phy-mode = "qsgmii";
385 			phy-handle = <&phy1>;
386 			phy-mode = "qsgmii";
392 			phy-handle = <&phy2>;
393 			phy-mode = "qsgmii";
399 			phy-handle = <&phy3>;
400 			phy-mode = "qsgmii";
406 			phy-handle = <&phy4>;
407 			phy-mode = "qsgmii";
413 			phy-handle = <&phy5>;
414 			phy-mode = "qsgmii";
420 			phy-handle = <&phy6>;
421 			phy-mode = "qsgmii";
427 			phy-handle = <&phy7>;
428 			phy-mode = "qsgmii";
434 			phy-handle = <&phy8>;
435 			phy-mode = "qsgmii";
441 			phy-handle = <&phy9>;
442 			phy-mode = "qsgmii";
448 			phy-handle = <&phy10>;
449 			phy-mode = "qsgmii";
455 			phy-handle = <&phy11>;
456 			phy-mode = "qsgmii";
462 			phy-handle = <&phy12>;
463 			phy-mode = "qsgmii";
469 			phy-handle = <&phy13>;
470 			phy-mode = "qsgmii";
476 			phy-handle = <&phy14>;
477 			phy-mode = "qsgmii";
483 			phy-handle = <&phy15>;
484 			phy-mode = "qsgmii";
490 			phy-handle = <&phy16>;
491 			phy-mode = "qsgmii";
497 			phy-handle = <&phy17>;
498 			phy-mode = "qsgmii";
504 			phy-handle = <&phy18>;
505 			phy-mode = "qsgmii";
511 			phy-handle = <&phy19>;
512 			phy-mode = "qsgmii";
518 			phy-handle = <&phy20>;
519 			phy-mode = "qsgmii";
525 			phy-handle = <&phy21>;
526 			phy-mode = "qsgmii";
532 			phy-handle = <&phy22>;
533 			phy-mode = "qsgmii";
539 			phy-handle = <&phy23>;
540 			phy-mode = "qsgmii";
546 			phy-handle = <&phy24>;
547 			phy-mode = "qsgmii";
553 			phy-handle = <&phy25>;
554 			phy-mode = "qsgmii";
560 			phy-handle = <&phy26>;
561 			phy-mode = "qsgmii";
567 			phy-handle = <&phy27>;
568 			phy-mode = "qsgmii";
574 			phy-handle = <&phy28>;
575 			phy-mode = "qsgmii";
581 			phy-handle = <&phy29>;
582 			phy-mode = "qsgmii";
588 			phy-handle = <&phy30>;
589 			phy-mode = "qsgmii";
595 			phy-handle = <&phy31>;
596 			phy-mode = "qsgmii";
602 			phy-handle = <&phy32>;
603 			phy-mode = "qsgmii";
609 			phy-handle = <&phy33>;
610 			phy-mode = "qsgmii";
616 			phy-handle = <&phy34>;
617 			phy-mode = "qsgmii";
623 			phy-handle = <&phy35>;
624 			phy-mode = "qsgmii";
630 			phy-handle = <&phy36>;
631 			phy-mode = "qsgmii";
637 			phy-handle = <&phy37>;
638 			phy-mode = "qsgmii";
644 			phy-handle = <&phy38>;
645 			phy-mode = "qsgmii";
651 			phy-handle = <&phy39>;
652 			phy-mode = "qsgmii";
658 			phy-handle = <&phy40>;
659 			phy-mode = "qsgmii";
665 			phy-handle = <&phy41>;
666 			phy-mode = "qsgmii";
672 			phy-handle = <&phy42>;
673 			phy-mode = "qsgmii";
679 			phy-handle = <&phy43>;
680 			phy-mode = "qsgmii";
686 			phy-handle = <&phy44>;
687 			phy-mode = "qsgmii";
693 			phy-handle = <&phy45>;
694 			phy-mode = "qsgmii";
700 			phy-handle = <&phy46>;
701 			phy-mode = "qsgmii";
707 			phy-handle = <&phy47>;
708 			phy-mode = "qsgmii";
715 			phy-mode = "10gbase-r";
717 			managed = "in-band-status";
723 			phy-mode = "10gbase-r";
725 			managed = "in-band-status";
731 			phy-mode = "10gbase-r";
733 			managed = "in-band-status";
739 			phy-mode = "10gbase-r";
741 			managed = "in-band-status";
748 			phy-handle = <&phy64>;
749 			phy-mode = "sgmii";