dts/microchip/sparx5_pcb134_board.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 	gpio-restart {
11 		compatible = "gpio-restart";
17 		compatible = "gpio-leds";
53 			default-state = "off";
58 			default-state = "off";
63 			default-state = "off";
68 			default-state = "off";
73 			default-state = "off";
78 			default-state = "off";
83 			default-state = "off";
88 			default-state = "off";
93 			default-state = "off";
98 			default-state = "off";
103 			default-state = "off";
108 			default-state = "off";
113 			default-state = "off";
118 			default-state = "off";
123 			default-state = "off";
128 			default-state = "off";
133 			default-state = "off";
138 			default-state = "off";
143 			default-state = "off";
148 			default-state = "off";
153 			default-state = "off";
158 			default-state = "off";
163 			default-state = "off";
168 			default-state = "off";
173 			default-state = "off";
178 			default-state = "off";
183 			default-state = "off";
188 			default-state = "off";
193 			default-state = "off";
198 			default-state = "off";
203 			default-state = "off";
208 			default-state = "off";
213 			default-state = "off";
218 			default-state = "off";
223 			default-state = "off";
228 			default-state = "off";
233 			default-state = "off";
238 			default-state = "off";
243 			default-state = "off";
248 			default-state = "off";
255 	microchip,sgpio-port-ranges = <8 15>;
266 	microchip,sgpio-port-ranges = <24 31>;
278 		compatible = "jedec,spi-nor";
279 		spi-max-frequency = <8000000>;
287 		compatible = "spi-mux";
288 		mux-controls = <&mux>;
289 		#address-cells = <1>;
290 		#size-cells = <0>;
293 			compatible = "jedec,spi-nor";
294 			spi-max-frequency = <8000000>;
302 	microchip,sgpio-port-ranges = <8 15>;
313 	microchip,sgpio-port-ranges = <24 31>;
324 	microchip,sgpio-port-ranges = <0 0>, <11 31>;
328 	i2cmux_pins_i: i2cmux-pins {
333 		output-low;
335 	i2cmux_0: i2cmux-0-pins {
338 		output-high;
340 	i2cmux_1: i2cmux-1-pins {
343 		output-high;
345 	i2cmux_2: i2cmux-2-pins {
348 		output-high;
350 	i2cmux_3: i2cmux-3-pins {
353 		output-high;
355 	i2cmux_4: i2cmux-4-pins {
358 		output-high;
360 	i2cmux_5: i2cmux-5-pins {
363 		output-high;
365 	i2cmux_6: i2cmux-6-pins {
368 		output-high;
370 	i2cmux_7: i2cmux-7-pins {
373 		output-high;
375 	i2cmux_8: i2cmux-8-pins {
378 		output-high;
380 	i2cmux_9: i2cmux-9-pins {
383 		output-high;
385 	i2cmux_10: i2cmux-10-pins {
388 		output-high;
390 	i2cmux_11: i2cmux-11-pins {
393 		output-high;
398 	i2c0_imux: i2c0-imux@0 {
399 		compatible = "i2c-mux-pinctrl";
400 		#address-cells = <1>;
401 		#size-cells = <0>;
402 		i2c-parent = <&i2c0>;
404 	i2c0_emux: i2c0-emux@0 {
405 		compatible = "i2c-mux-gpio";
406 		#address-cells = <1>;
407 		#size-cells = <0>;
408 		i2c-parent = <&i2c0>;
413 	pinctrl-names =
417 	pinctrl-0 = <&i2cmux_0>;
418 	pinctrl-1 = <&i2cmux_1>;
419 	pinctrl-2 = <&i2cmux_2>;
420 	pinctrl-3 = <&i2cmux_3>;
421 	pinctrl-4 = <&i2cmux_4>;
422 	pinctrl-5 = <&i2cmux_5>;
423 	pinctrl-6 = <&i2cmux_6>;
424 	pinctrl-7 = <&i2cmux_7>;
425 	pinctrl-8 = <&i2cmux_8>;
426 	pinctrl-9 = <&i2cmux_9>;
427 	pinctrl-10 = <&i2cmux_10>;
428 	pinctrl-11 = <&i2cmux_11>;
429 	pinctrl-12 = <&i2cmux_pins_i>;
432 		#address-cells = <1>;
433 		#size-cells = <0>;
437 		#address-cells = <1>;
438 		#size-cells = <0>;
442 		#address-cells = <1>;
443 		#size-cells = <0>;
447 		#address-cells = <1>;
448 		#size-cells = <0>;
452 		#address-cells = <1>;
453 		#size-cells = <0>;
457 		#address-cells = <1>;
458 		#size-cells = <0>;
462 		#address-cells = <1>;
463 		#size-cells = <0>;
467 		#address-cells = <1>;
468 		#size-cells = <0>;
472 		#address-cells = <1>;
473 		#size-cells = <0>;
477 		#address-cells = <1>;
478 		#size-cells = <0>;
482 		#address-cells = <1>;
483 		#size-cells = <0>;
487 		#address-cells = <1>;
488 		#size-cells = <0>;
493 	mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH
497 	idle-state = <0x8>;
500 		#address-cells = <1>;
501 		#size-cells = <0>;
505 		#address-cells = <1>;
506 		#size-cells = <0>;
510 		#address-cells = <1>;
511 		#size-cells = <0>;
515 		#address-cells = <1>;
516 		#size-cells = <0>;
520 		#address-cells = <1>;
521 		#size-cells = <0>;
525 		#address-cells = <1>;
526 		#size-cells = <0>;
530 		#address-cells = <1>;
531 		#size-cells = <0>;
535 		#address-cells = <1>;
536 		#size-cells = <0>;
542 	phy64: ethernet-phy@64 {
548 	sfp_eth12: sfp-eth12 {
550 		i2c-bus = <&i2c_sfp1>;
551 		tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>;
552 		los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>;
553 		mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>;
554 		tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>;
556 	sfp_eth13: sfp-eth13 {
558 		i2c-bus = <&i2c_sfp2>;
559 		tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>;
560 		los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>;
561 		mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>;
562 		tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>;
564 	sfp_eth14: sfp-eth14 {
566 		i2c-bus = <&i2c_sfp3>;
567 		tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>;
568 		los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>;
569 		mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>;
570 		tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>;
572 	sfp_eth15: sfp-eth15 {
574 		i2c-bus = <&i2c_sfp4>;
575 		tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>;
576 		los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>;
577 		mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>;
578 		tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>;
580 	sfp_eth48: sfp-eth48 {
582 		i2c-bus = <&i2c_sfp5>;
583 		tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>;
584 		los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>;
585 		mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>;
586 		tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>;
588 	sfp_eth49: sfp-eth49 {
590 		i2c-bus = <&i2c_sfp6>;
591 		tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>;
592 		los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>;
593 		mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>;
594 		tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>;
596 	sfp_eth50: sfp-eth50 {
598 		i2c-bus = <&i2c_sfp7>;
599 		tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>;
600 		los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>;
601 		mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>;
602 		tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>;
604 	sfp_eth51: sfp-eth51 {
606 		i2c-bus = <&i2c_sfp8>;
607 		tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>;
608 		los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>;
609 		mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>;
610 		tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>;
612 	sfp_eth52: sfp-eth52 {
614 		i2c-bus = <&i2c_sfp9>;
615 		tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>;
616 		los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>;
617 		mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>;
618 		tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>;
620 	sfp_eth53: sfp-eth53 {
622 		i2c-bus = <&i2c_sfp10>;
623 		tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>;
624 		los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>;
625 		mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>;
626 		tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>;
628 	sfp_eth54: sfp-eth54 {
630 		i2c-bus = <&i2c_sfp11>;
631 		tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>;
632 		los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>;
633 		mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>;
634 		tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>;
636 	sfp_eth55: sfp-eth55 {
638 		i2c-bus = <&i2c_sfp12>;
639 		tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>;
640 		los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>;
641 		mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>;
642 		tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>;
644 	sfp_eth56: sfp-eth56 {
646 		i2c-bus = <&i2c_sfp13>;
647 		tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>;
648 		los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>;
649 		mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>;
650 		tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>;
652 	sfp_eth57: sfp-eth57 {
654 		i2c-bus = <&i2c_sfp14>;
655 		tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>;
656 		los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>;
657 		mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>;
658 		tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>;
660 	sfp_eth58: sfp-eth58 {
662 		i2c-bus = <&i2c_sfp15>;
663 		tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>;
664 		los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>;
665 		mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>;
666 		tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>;
668 	sfp_eth59: sfp-eth59 {
670 		i2c-bus = <&i2c_sfp16>;
671 		tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>;
672 		los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>;
673 		mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>;
674 		tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>;
676 	sfp_eth60: sfp-eth60 {
678 		i2c-bus = <&i2c_sfp17>;
679 		tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>;
680 		los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>;
681 		mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>;
682 		tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
684 	sfp_eth61: sfp-eth61 {
686 		i2c-bus = <&i2c_sfp18>;
687 		tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>;
688 		los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>;
689 		mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>;
690 		tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
692 	sfp_eth62: sfp-eth62 {
694 		i2c-bus = <&i2c_sfp19>;
695 		tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>;
696 		los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>;
697 		mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>;
698 		tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
700 	sfp_eth63: sfp-eth63 {
702 		i2c-bus = <&i2c_sfp20>;
703 		tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>;
704 		los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>;
705 		mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>;
706 		tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
711 	ethernet-ports {
712 		#address-cells = <1>;
713 		#size-cells = <0>;
720 			phy-mode = "10gbase-r";
722 			microchip,sd-sgpio = <301>;
723 			managed = "in-band-status";
730 			phy-mode = "10gbase-r";
732 			microchip,sd-sgpio = <305>;
733 			managed = "in-band-status";
739 			phy-mode = "10gbase-r";
741 			microchip,sd-sgpio = <309>;
742 			managed = "in-band-status";
748 			phy-mode = "10gbase-r";
750 			microchip,sd-sgpio = <313>;
751 			managed = "in-band-status";
757 			phy-mode = "10gbase-r";
759 			microchip,sd-sgpio = <317>;
760 			managed = "in-band-status";
766 			phy-mode = "10gbase-r";
768 			microchip,sd-sgpio = <321>;
769 			managed = "in-band-status";
775 			phy-mode = "10gbase-r";
777 			microchip,sd-sgpio = <325>;
778 			managed = "in-band-status";
784 			phy-mode = "10gbase-r";
786 			microchip,sd-sgpio = <329>;
787 			managed = "in-band-status";
793 			phy-mode = "10gbase-r";
795 			microchip,sd-sgpio = <333>;
796 			managed = "in-band-status";
802 			phy-mode = "10gbase-r";
804 			microchip,sd-sgpio = <337>;
805 			managed = "in-band-status";
811 			phy-mode = "10gbase-r";
813 			microchip,sd-sgpio = <341>;
814 			managed = "in-band-status";
820 			phy-mode = "10gbase-r";
822 			microchip,sd-sgpio = <345>;
823 			managed = "in-band-status";
830 			phy-mode = "10gbase-r";
832 			microchip,sd-sgpio = <349>;
833 			managed = "in-band-status";
839 			phy-mode = "10gbase-r";
841 			microchip,sd-sgpio = <353>;
842 			managed = "in-band-status";
848 			phy-mode = "10gbase-r";
850 			microchip,sd-sgpio = <357>;
851 			managed = "in-band-status";
857 			phy-mode = "10gbase-r";
859 			microchip,sd-sgpio = <361>;
860 			managed = "in-band-status";
866 			phy-mode = "10gbase-r";
868 			microchip,sd-sgpio = <365>;
869 			managed = "in-band-status";
875 			phy-mode = "10gbase-r";
877 			microchip,sd-sgpio = <369>;
878 			managed = "in-band-status";
884 			phy-mode = "10gbase-r";
886 			microchip,sd-sgpio = <373>;
887 			managed = "in-band-status";
893 			phy-mode = "10gbase-r";
895 			microchip,sd-sgpio = <377>;
896 			managed = "in-band-status";
903 			phy-handle = <&phy64>;
904 			phy-mode = "sgmii";