Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mediatek,mt8365-power.h>
16 interrupt-parent = <&sysirq>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cluster0_opp: opp-table-0 {
25 compatible = "operating-points-v2";
26 opp-shared;
28 opp-850000000 {
29 opp-hz = /bits/ 64 <850000000>;
30 opp-microvolt = <650000>;
33 opp-918000000 {
34 opp-hz = /bits/ 64 <918000000>;
35 opp-microvolt = <668750>;
38 opp-987000000 {
39 opp-hz = /bits/ 64 <987000000>;
40 opp-microvolt = <687500>;
43 opp-1056000000 {
44 opp-hz = /bits/ 64 <1056000000>;
45 opp-microvolt = <706250>;
48 opp-1125000000 {
49 opp-hz = /bits/ 64 <1125000000>;
50 opp-microvolt = <725000>;
53 opp-1216000000 {
54 opp-hz = /bits/ 64 <1216000000>;
55 opp-microvolt = <750000>;
58 opp-1308000000 {
59 opp-hz = /bits/ 64 <1308000000>;
60 opp-microvolt = <775000>;
63 opp-1400000000 {
64 opp-hz = /bits/ 64 <1400000000>;
65 opp-microvolt = <800000>;
68 opp-1466000000 {
69 opp-hz = /bits/ 64 <1466000000>;
70 opp-microvolt = <825000>;
73 opp-1533000000 {
74 opp-hz = /bits/ 64 <1533000000>;
75 opp-microvolt = <850000>;
78 opp-1633000000 {
79 opp-hz = /bits/ 64 <1633000000>;
80 opp-microvolt = <887500>;
83 opp-1700000000 {
84 opp-hz = /bits/ 64 <1700000000>;
85 opp-microvolt = <912500>;
88 opp-1767000000 {
89 opp-hz = /bits/ 64 <1767000000>;
90 opp-microvolt = <937500>;
93 opp-1834000000 {
94 opp-hz = /bits/ 64 <1834000000>;
95 opp-microvolt = <962500>;
98 opp-1917000000 {
99 opp-hz = /bits/ 64 <1917000000>;
100 opp-microvolt = <993750>;
103 opp-2001000000 {
104 opp-hz = /bits/ 64 <2001000000>;
105 opp-microvolt = <1025000>;
109 cpu-map {
128 compatible = "arm,cortex-a53";
130 #cooling-cells = <2>;
131 enable-method = "psci";
132 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
133 i-cache-size = <0x8000>;
134 i-cache-line-size = <64>;
135 i-cache-sets = <256>;
136 d-cache-size = <0x8000>;
137 d-cache-line-size = <64>;
138 d-cache-sets = <256>;
139 next-level-cache = <&l2>;
142 clock-names = "cpu", "intermediate";
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a53";
150 #cooling-cells = <2>;
151 enable-method = "psci";
152 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
153 i-cache-size = <0x8000>;
154 i-cache-line-size = <64>;
155 i-cache-sets = <256>;
156 d-cache-size = <0x8000>;
157 d-cache-line-size = <64>;
158 d-cache-sets = <256>;
159 next-level-cache = <&l2>;
162 clock-names = "cpu", "intermediate", "armpll";
163 operating-points-v2 = <&cluster0_opp>;
168 compatible = "arm,cortex-a53";
170 #cooling-cells = <2>;
171 enable-method = "psci";
172 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
173 i-cache-size = <0x8000>;
174 i-cache-line-size = <64>;
175 i-cache-sets = <256>;
176 d-cache-size = <0x8000>;
177 d-cache-line-size = <64>;
178 d-cache-sets = <256>;
179 next-level-cache = <&l2>;
182 clock-names = "cpu", "intermediate", "armpll";
183 operating-points-v2 = <&cluster0_opp>;
188 compatible = "arm,cortex-a53";
190 #cooling-cells = <2>;
191 enable-method = "psci";
192 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
193 i-cache-size = <0x8000>;
194 i-cache-line-size = <64>;
195 i-cache-sets = <256>;
196 d-cache-size = <0x8000>;
197 d-cache-line-size = <64>;
198 d-cache-sets = <256>;
199 next-level-cache = <&l2>;
202 clock-names = "cpu", "intermediate", "armpll";
203 operating-points-v2 = <&cluster0_opp>;
206 idle-states {
207 entry-method = "psci";
209 CPU_MCDI: cpu-mcdi {
210 compatible = "arm,idle-state";
211 local-timer-stop;
212 arm,psci-suspend-param = <0x00010001>;
213 entry-latency-us = <300>;
214 exit-latency-us = <200>;
215 min-residency-us = <1000>;
218 CLUSTER_MCDI: cluster-mcdi {
219 compatible = "arm,idle-state";
220 local-timer-stop;
221 arm,psci-suspend-param = <0x01010001>;
222 entry-latency-us = <350>;
223 exit-latency-us = <250>;
224 min-residency-us = <1200>;
227 CLUSTER_DPIDLE: cluster-dpidle {
228 compatible = "arm,idle-state";
229 local-timer-stop;
230 arm,psci-suspend-param = <0x01010004>;
231 entry-latency-us = <300>;
232 exit-latency-us = <800>;
233 min-residency-us = <3300>;
237 l2: l2-cache {
239 cache-level = <2>;
240 cache-size = <0x80000>;
241 cache-line-size = <64>;
242 cache-sets = <512>;
243 cache-unified;
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <26000000>;
251 clock-output-names = "clk26m";
254 psci {
255 compatible = "arm,psci-1.0";
260 #address-cells = <2>;
261 #size-cells = <2>;
262 compatible = "simple-bus";
265 gic: interrupt-controller@c000000 {
266 compatible = "arm,gic-v3";
267 #interrupt-cells = <3>;
268 interrupt-parent = <&gic>;
269 interrupt-controller;
280 compatible = "mediatek,mt8365-topckgen", "syscon";
282 #clock-cells = <1>;
286 compatible = "mediatek,mt8365-infracfg", "syscon";
288 #clock-cells = <1>;
292 compatible = "mediatek,mt8365-pericfg", "syscon";
294 #clock-cells = <1>;
297 syscfg_pctl: syscfg-pctl@10005000 {
298 compatible = "mediatek,mt8365-syscfg", "syscon";
303 compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
305 #power-domain-cells = <1>;
308 spm: power-controller {
309 compatible = "mediatek,mt8365-power-controller";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 #power-domain-cells = <1>;
315 power-domain@MT8365_POWER_DOMAIN_MM {
322 clock-names = "mm", "mm-0", "mm-1",
323 "mm-2", "mm-3";
324 #power-domain-cells = <0>;
326 mediatek,infracfg-nao = <&infracfg_nao>;
327 #address-cells = <1>;
328 #size-cells = <0>;
330 power-domain@MT8365_POWER_DOMAIN_CAM {
338 clock-names = "cam-0", "cam-1",
339 "cam-2", "cam-3",
340 "cam-4", "cam-5";
341 #power-domain-cells = <0>;
346 power-domain@MT8365_POWER_DOMAIN_VDEC {
348 #power-domain-cells = <0>;
352 power-domain@MT8365_POWER_DOMAIN_VENC {
354 #power-domain-cells = <0>;
358 power-domain@MT8365_POWER_DOMAIN_APU {
367 clock-names = "apu", "apu-0",
368 "apu-1", "apu-2",
369 "apu-3", "apu-4",
370 "apu-5";
371 #power-domain-cells = <0>;
377 power-domain@MT8365_POWER_DOMAIN_CONN {
381 clock-names = "conn", "conn1";
382 #power-domain-cells = <0>;
386 power-domain@MT8365_POWER_DOMAIN_MFG {
389 clock-names = "mfg";
390 #power-domain-cells = <0>;
394 power-domain@MT8365_POWER_DOMAIN_AUDIO {
399 clock-names = "audio", "audio1", "audio2";
400 #power-domain-cells = <0>;
404 power-domain@MT8365_POWER_DOMAIN_DSP {
408 clock-names = "dsp", "dsp1";
409 #power-domain-cells = <0>;
416 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
418 #reset-cells = <1>;
422 compatible = "mediatek,mt8365-pinctrl";
424 mediatek,pctl-regmap = <&syscfg_pctl>;
425 gpio-controller;
426 #gpio-cells = <2>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
433 compatible = "mediatek,mt8365-apmixedsys", "syscon";
435 #clock-cells = <1>;
439 compatible = "mediatek,mt8365-pwrap";
441 reg-names = "pwrap";
447 clock-names = "spi", "wrap", "sys", "tmr";
451 compatible = "mediatek,mt6779-keypad";
453 wakeup-source;
456 clock-names = "kpd";
461 compatible = "mediatek,mt8365-mcucfg", "syscon";
463 #clock-cells = <1>;
466 sysirq: interrupt-controller@10200a80 {
467 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
468 interrupt-controller;
469 #interrupt-cells = <3>;
470 interrupt-parent = <&gic>;
475 compatible = "mediatek,mt8365-m4u";
479 #iommu-cells = <1>;
483 compatible = "mediatek,mt8365-infracfg", "syscon";
485 #clock-cells = <1>;
489 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
492 clock-names = "rng";
495 apdma: dma-controller@11000280 {
496 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
509 dma-requests = <6>;
511 clock-names = "apdma";
512 #dma-cells = <1>;
516 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
520 clock-names = "baud", "bus";
522 dma-names = "tx", "rx";
527 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
531 clock-names = "baud", "bus";
533 dma-names = "tx", "rx";
538 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
542 clock-names = "baud", "bus";
544 dma-names = "tx", "rx";
549 compatible = "mediatek,mt8365-pwm";
551 #pwm-cells = <2>;
558 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
562 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
565 clock-div = <1>;
567 clock-names = "main", "dma";
568 #address-cells = <1>;
569 #size-cells = <0>;
574 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
577 clock-div = <1>;
579 clock-names = "main", "dma";
580 #address-cells = <1>;
581 #size-cells = <0>;
586 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
589 clock-div = <1>;
591 clock-names = "main", "dma";
592 #address-cells = <1>;
593 #size-cells = <0>;
598 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
600 #address-cells = <1>;
601 #size-cells = <0>;
606 clock-names = "parent-clk", "sel-clk", "spi-clk";
611 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
614 clock-div = <1>;
616 clock-names = "main", "dma";
617 #address-cells = <1>;
618 #size-cells = <0>;
623 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
625 reg-names = "mac", "ippc";
633 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
634 #address-cells = <2>;
635 #size-cells = <2>;
640 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
642 reg-names = "mac";
649 clock-names = "sys_ck", "ref_ck", "mcu_ck",
656 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
663 clock-names = "source", "hclk", "source_cg";
668 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
675 clock-names = "source", "hclk", "source_cg";
680 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
689 clock-names = "source", "hclk", "source_cg",
695 compatible = "mediatek,mt8365-eth";
702 clock-names = "core", "reg", "trans";
706 u3phy: t-phy@11cc0000 {
707 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
708 #address-cells = <1>;
709 #size-cells = <1>;
712 u2port0: usb-phy@0 {
716 clock-names = "ref", "da_ref";
717 #phy-cells = <1>;
720 u2port1: usb-phy@1000 {
724 clock-names = "ref", "da_ref";
725 #phy-cells = <1>;
730 compatible = "mediatek,mt8365-mmsys", "syscon";
732 #clock-cells = <1>;
736 compatible = "mediatek,mt8365-smi-common";
742 clock-names = "apb", "smi", "gals0", "gals1";
743 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
747 compatible = "mediatek,mt8365-smi-larb",
748 "mediatek,mt8186-smi-larb";
753 clock-names = "apb", "smi";
754 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
755 mediatek,larb-id = <0>;
759 compatible = "mediatek,mt8365-imgsys", "syscon";
761 #clock-cells = <1>;
765 compatible = "mediatek,mt8365-smi-larb",
766 "mediatek,mt8186-smi-larb";
771 clock-names = "apb", "smi";
772 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
773 mediatek,larb-id = <2>;
777 compatible = "mediatek,mt8365-vdecsys", "syscon";
779 #clock-cells = <1>;
783 compatible = "mediatek,mt8365-smi-larb",
784 "mediatek,mt8186-smi-larb";
789 clock-names = "apb", "smi";
790 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
791 mediatek,larb-id = <3>;
795 compatible = "mediatek,mt8365-vencsys", "syscon";
797 #clock-cells = <1>;
801 compatible = "mediatek,mt8365-smi-larb",
802 "mediatek,mt8186-smi-larb";
806 clock-names = "apb", "smi";
807 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
808 mediatek,larb-id = <1>;
812 compatible = "mediatek,mt8365-apu", "syscon";
814 #clock-cells = <1>;
819 compatible = "arm,armv8-timer";
820 interrupt-parent = <&gic>;
828 compatible = "fixed-clock";
829 clock-frequency = <13000000>;
830 #clock-cells = <0>;
834 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
838 clock-names = "clk13m";