Lines Matching +full:entry +full:- +full:latency +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
13 #include <dt-bindings/power/mediatek,mt8188-power.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a55";
29 enable-method = "psci";
30 clock-frequency = <2000000000>;
31 capacity-dmips-mhz = <282>;
32 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
33 i-cache-size = <32768>;
34 i-cache-line-size = <64>;
35 i-cache-sets = <128>;
36 d-cache-size = <32768>;
37 d-cache-line-size = <64>;
38 d-cache-sets = <128>;
39 next-level-cache = <&l2_0>;
40 #cooling-cells = <2>;
45 compatible = "arm,cortex-a55";
47 enable-method = "psci";
48 clock-frequency = <2000000000>;
49 capacity-dmips-mhz = <282>;
50 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
51 i-cache-size = <32768>;
52 i-cache-line-size = <64>;
53 i-cache-sets = <128>;
54 d-cache-size = <32768>;
55 d-cache-line-size = <64>;
56 d-cache-sets = <128>;
57 next-level-cache = <&l2_0>;
58 #cooling-cells = <2>;
63 compatible = "arm,cortex-a55";
65 enable-method = "psci";
66 clock-frequency = <2000000000>;
67 capacity-dmips-mhz = <282>;
68 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
69 i-cache-size = <32768>;
70 i-cache-line-size = <64>;
71 i-cache-sets = <128>;
72 d-cache-size = <32768>;
73 d-cache-line-size = <64>;
74 d-cache-sets = <128>;
75 next-level-cache = <&l2_0>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a55";
83 enable-method = "psci";
84 clock-frequency = <2000000000>;
85 capacity-dmips-mhz = <282>;
86 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
87 i-cache-size = <32768>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <128>;
90 d-cache-size = <32768>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&l2_0>;
94 #cooling-cells = <2>;
99 compatible = "arm,cortex-a55";
101 enable-method = "psci";
102 clock-frequency = <2000000000>;
103 capacity-dmips-mhz = <282>;
104 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
105 i-cache-size = <32768>;
106 i-cache-line-size = <64>;
107 i-cache-sets = <128>;
108 d-cache-size = <32768>;
109 d-cache-line-size = <64>;
110 d-cache-sets = <128>;
111 next-level-cache = <&l2_0>;
112 #cooling-cells = <2>;
117 compatible = "arm,cortex-a55";
119 enable-method = "psci";
120 clock-frequency = <2000000000>;
121 capacity-dmips-mhz = <282>;
122 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
123 i-cache-size = <32768>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <128>;
126 d-cache-size = <32768>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <128>;
129 next-level-cache = <&l2_0>;
130 #cooling-cells = <2>;
135 compatible = "arm,cortex-a78";
137 enable-method = "psci";
138 clock-frequency = <2600000000>;
139 capacity-dmips-mhz = <1024>;
140 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
141 i-cache-size = <65536>;
142 i-cache-line-size = <64>;
143 i-cache-sets = <256>;
144 d-cache-size = <65536>;
145 d-cache-line-size = <64>;
146 d-cache-sets = <256>;
147 next-level-cache = <&l2_1>;
148 #cooling-cells = <2>;
153 compatible = "arm,cortex-a78";
155 enable-method = "psci";
156 clock-frequency = <2600000000>;
157 capacity-dmips-mhz = <1024>;
158 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
159 i-cache-size = <65536>;
160 i-cache-line-size = <64>;
161 i-cache-sets = <256>;
162 d-cache-size = <65536>;
163 d-cache-line-size = <64>;
164 d-cache-sets = <256>;
165 next-level-cache = <&l2_1>;
166 #cooling-cells = <2>;
169 cpu-map {
205 idle-states {
206 entry-method = "psci";
208 cpu_off_l: cpu-off-l {
209 compatible = "arm,idle-state";
210 arm,psci-suspend-param = <0x00010000>;
211 local-timer-stop;
212 entry-latency-us = <50>;
213 exit-latency-us = <95>;
214 min-residency-us = <580>;
217 cpu_off_b: cpu-off-b {
218 compatible = "arm,idle-state";
219 arm,psci-suspend-param = <0x00010000>;
220 local-timer-stop;
221 entry-latency-us = <45>;
222 exit-latency-us = <140>;
223 min-residency-us = <740>;
226 cluster_off_l: cluster-off-l {
227 compatible = "arm,idle-state";
228 arm,psci-suspend-param = <0x01010010>;
229 local-timer-stop;
230 entry-latency-us = <55>;
231 exit-latency-us = <155>;
232 min-residency-us = <840>;
235 cluster_off_b: cluster-off-b {
236 compatible = "arm,idle-state";
237 arm,psci-suspend-param = <0x01010010>;
238 local-timer-stop;
239 entry-latency-us = <50>;
240 exit-latency-us = <200>;
241 min-residency-us = <1000>;
245 l2_0: l2-cache0 {
247 cache-level = <2>;
248 cache-size = <131072>;
249 cache-line-size = <64>;
250 cache-sets = <512>;
251 next-level-cache = <&l3_0>;
252 cache-unified;
255 l2_1: l2-cache1 {
257 cache-level = <2>;
258 cache-size = <262144>;
259 cache-line-size = <64>;
260 cache-sets = <512>;
261 next-level-cache = <&l3_0>;
262 cache-unified;
265 l3_0: l3-cache {
267 cache-level = <3>;
268 cache-size = <2097152>;
269 cache-line-size = <64>;
270 cache-sets = <2048>;
271 cache-unified;
275 clk13m: oscillator-13m {
276 compatible = "fixed-clock";
277 #clock-cells = <0>;
278 clock-frequency = <13000000>;
279 clock-output-names = "clk13m";
282 clk26m: oscillator-26m {
283 compatible = "fixed-clock";
284 #clock-cells = <0>;
285 clock-frequency = <26000000>;
286 clock-output-names = "clk26m";
289 clk32k: oscillator-32k {
290 compatible = "fixed-clock";
291 #clock-cells = <0>;
292 clock-frequency = <32768>;
293 clock-output-names = "clk32k";
296 pmu-a55 {
297 compatible = "arm,cortex-a55-pmu";
298 interrupt-parent = <&gic>;
302 pmu-a78 {
303 compatible = "arm,cortex-a78-pmu";
304 interrupt-parent = <&gic>;
309 compatible = "arm,psci-1.0";
314 compatible = "arm,armv8-timer";
315 interrupt-parent = <&gic>;
320 clock-frequency = <13000000>;
324 #address-cells = <2>;
325 #size-cells = <2>;
326 compatible = "simple-bus";
329 gic: interrupt-controller@c000000 {
330 compatible = "arm,gic-v3";
331 #interrupt-cells = <4>;
332 #redistributor-regions = <1>;
333 interrupt-parent = <&gic>;
334 interrupt-controller;
339 ppi-partitions {
340 ppi_cluster0: interrupt-partition-0 {
344 ppi_cluster1: interrupt-partition-1 {
351 compatible = "mediatek,mt8188-topckgen", "syscon";
353 #clock-cells = <1>;
357 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
359 #clock-cells = <1>;
363 compatible = "mediatek,mt8188-pericfg", "syscon";
365 #clock-cells = <1>;
369 compatible = "mediatek,mt8188-pinctrl";
376 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
378 gpio-controller;
379 #gpio-cells = <2>;
380 gpio-ranges = <&pio 0 0 176>;
381 interrupt-controller;
383 #interrupt-cells = <2>;
387 compatible = "mediatek,mt8188-wdt";
389 mediatek,disable-extrst;
390 #reset-cells = <1>;
394 compatible = "mediatek,mt8188-apmixedsys", "syscon";
396 #clock-cells = <1>;
400 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
407 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
409 reg-names = "pwrap";
413 clock-names = "spi", "wrap";
417 compatible = "mediatek,mt8188-scp";
420 reg-names = "sram", "cfg";
424 adsp_audio26m: clock-controller@10b91100 {
425 compatible = "mediatek,mt8188-adsp-audio26m";
427 #clock-cells = <1>;
431 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
435 clock-names = "baud", "bus";
440 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
444 clock-names = "baud", "bus";
449 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
453 clock-names = "baud", "bus";
458 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
462 clock-names = "baud", "bus";
467 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
470 clock-names = "main";
471 #io-channel-cells = <1>;
476 compatible = "mediatek,mt8188-pericfg-ao", "syscon";
478 #clock-cells = <1>;
482 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
483 #address-cells = <1>;
484 #size-cells = <0>;
490 clock-names = "parent-clk", "sel-clk", "spi-clk";
495 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
496 #address-cells = <1>;
497 #size-cells = <0>;
503 clock-names = "parent-clk", "sel-clk", "spi-clk";
508 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
509 #address-cells = <1>;
510 #size-cells = <0>;
516 clock-names = "parent-clk", "sel-clk", "spi-clk";
521 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
522 #address-cells = <1>;
523 #size-cells = <0>;
529 clock-names = "parent-clk", "sel-clk", "spi-clk";
534 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
535 #address-cells = <1>;
536 #size-cells = <0>;
542 clock-names = "parent-clk", "sel-clk", "spi-clk";
547 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
548 #address-cells = <1>;
549 #size-cells = <0>;
555 clock-names = "parent-clk", "sel-clk", "spi-clk";
560 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
563 reg-names = "mac", "ippc";
567 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
569 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
574 clock-names = "sys_ck", "ref_ck", "mcu_ck";
575 mediatek,syscon-wakeup = <&pericfg 0x468 2>;
576 wakeup-source;
581 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
589 clock-names = "source", "hclk", "source_cg", "crypto_clk";
594 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
601 clock-names = "source", "hclk", "source_cg";
602 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
603 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
608 compatible = "mediatek,mt8188-i2c";
612 clock-div = <1>;
615 clock-names = "main", "dma";
616 #address-cells = <1>;
617 #size-cells = <0>;
622 compatible = "mediatek,mt8188-i2c";
626 clock-div = <1>;
629 clock-names = "main", "dma";
630 #address-cells = <1>;
631 #size-cells = <0>;
636 compatible = "mediatek,mt8188-i2c";
640 clock-div = <1>;
643 clock-names = "main", "dma";
644 #address-cells = <1>;
645 #size-cells = <0>;
649 imp_iic_wrap_c: clock-controller@11283000 {
650 compatible = "mediatek,mt8188-imp-iic-wrap-c";
652 #clock-cells = <1>;
656 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
659 reg-names = "mac", "ippc";
662 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
664 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
669 clock-names = "sys_ck", "ref_ck", "mcu_ck";
674 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
677 reg-names = "mac", "ippc";
680 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
682 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
687 clock-names = "sys_ck", "ref_ck", "mcu_ck";
688 mediatek,syscon-wakeup = <&pericfg 0x460 2>;
689 wakeup-source;
694 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
699 clock-names = "spi", "sf", "axi";
700 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
706 compatible = "mediatek,mt8188-i2c";
710 clock-div = <1>;
713 clock-names = "main", "dma";
714 #address-cells = <1>;
715 #size-cells = <0>;
720 compatible = "mediatek,mt8188-i2c";
724 clock-div = <1>;
727 clock-names = "main", "dma";
728 #address-cells = <1>;
729 #size-cells = <0>;
733 imp_iic_wrap_w: clock-controller@11e02000 {
734 compatible = "mediatek,mt8188-imp-iic-wrap-w";
736 #clock-cells = <1>;
739 u3phy0: t-phy@11e30000 {
740 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
741 #address-cells = <1>;
742 #size-cells = <1>;
746 u2port0: usb-phy@0 {
750 clock-names = "ref", "da_ref";
751 #phy-cells = <1>;
755 u3phy1: t-phy@11e40000 {
756 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
757 #address-cells = <1>;
758 #size-cells = <1>;
762 u2port1: usb-phy@0 {
766 clock-names = "ref", "da_ref";
767 #phy-cells = <1>;
770 u3port1: usb-phy@700 {
774 clock-names = "ref", "da_ref";
775 #phy-cells = <1>;
780 u3phy2: t-phy@11e80000 {
781 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
782 #address-cells = <1>;
783 #size-cells = <1>;
787 u2port2: usb-phy@0 {
791 clock-names = "ref", "da_ref";
792 #phy-cells = <1>;
797 compatible = "mediatek,mt8188-i2c";
801 clock-div = <1>;
804 clock-names = "main", "dma";
805 #address-cells = <1>;
806 #size-cells = <0>;
811 compatible = "mediatek,mt8188-i2c";
815 clock-div = <1>;
818 clock-names = "main", "dma";
819 #address-cells = <1>;
820 #size-cells = <0>;
824 imp_iic_wrap_en: clock-controller@11ec2000 {
825 compatible = "mediatek,mt8188-imp-iic-wrap-en";
827 #clock-cells = <1>;
830 mfgcfg: clock-controller@13fbf000 {
831 compatible = "mediatek,mt8188-mfgcfg";
833 #clock-cells = <1>;
836 vppsys0: clock-controller@14000000 {
837 compatible = "mediatek,mt8188-vppsys0";
839 #clock-cells = <1>;
842 wpesys: clock-controller@14e00000 {
843 compatible = "mediatek,mt8188-wpesys";
845 #clock-cells = <1>;
848 wpesys_vpp0: clock-controller@14e02000 {
849 compatible = "mediatek,mt8188-wpesys-vpp0";
851 #clock-cells = <1>;
854 vppsys1: clock-controller@14f00000 {
855 compatible = "mediatek,mt8188-vppsys1";
857 #clock-cells = <1>;
860 imgsys: clock-controller@15000000 {
861 compatible = "mediatek,mt8188-imgsys";
863 #clock-cells = <1>;
866 imgsys1_dip_top: clock-controller@15110000 {
867 compatible = "mediatek,mt8188-imgsys1-dip-top";
869 #clock-cells = <1>;
872 imgsys1_dip_nr: clock-controller@15130000 {
873 compatible = "mediatek,mt8188-imgsys1-dip-nr";
875 #clock-cells = <1>;
878 imgsys_wpe1: clock-controller@15220000 {
879 compatible = "mediatek,mt8188-imgsys-wpe1";
881 #clock-cells = <1>;
884 ipesys: clock-controller@15330000 {
885 compatible = "mediatek,mt8188-ipesys";
887 #clock-cells = <1>;
890 imgsys_wpe2: clock-controller@15520000 {
891 compatible = "mediatek,mt8188-imgsys-wpe2";
893 #clock-cells = <1>;
896 imgsys_wpe3: clock-controller@15620000 {
897 compatible = "mediatek,mt8188-imgsys-wpe3";
899 #clock-cells = <1>;
902 camsys: clock-controller@16000000 {
903 compatible = "mediatek,mt8188-camsys";
905 #clock-cells = <1>;
908 camsys_rawa: clock-controller@1604f000 {
909 compatible = "mediatek,mt8188-camsys-rawa";
911 #clock-cells = <1>;
914 camsys_yuva: clock-controller@1606f000 {
915 compatible = "mediatek,mt8188-camsys-yuva";
917 #clock-cells = <1>;
920 camsys_rawb: clock-controller@1608f000 {
921 compatible = "mediatek,mt8188-camsys-rawb";
923 #clock-cells = <1>;
926 camsys_yuvb: clock-controller@160af000 {
927 compatible = "mediatek,mt8188-camsys-yuvb";
929 #clock-cells = <1>;
932 ccusys: clock-controller@17200000 {
933 compatible = "mediatek,mt8188-ccusys";
935 #clock-cells = <1>;
938 vdecsys_soc: clock-controller@1800f000 {
939 compatible = "mediatek,mt8188-vdecsys-soc";
941 #clock-cells = <1>;
944 vdecsys: clock-controller@1802f000 {
945 compatible = "mediatek,mt8188-vdecsys";
947 #clock-cells = <1>;
950 vencsys: clock-controller@1a000000 {
951 compatible = "mediatek,mt8188-vencsys";
953 #clock-cells = <1>;