dts/intel/socfpga_n5x_socdk.dts

1 // SPDX-License-Identifier:     GPL-2.0
9 	compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 		stdout-path = "serial0:115200n8";
29 		sdram_edac: memory-controller@f87f8000 {
30 			compatible = "snps,ddrc-3.80a";
38 	compatible = "intel,easic-n5x-clkmgr";
43 	phy-mode = "rgmii";
44 	phy-handle = <&phy0>;
46 	max-frame-size = <9000>;
49 		#address-cells = <1>;
50 		#size-cells = <0>;
51 		compatible = "snps,dwmac-mdio";
52 		phy0: ethernet-phy@0 {
55 			txd0-skew-ps = <0>; /* -420ps */
56 			txd1-skew-ps = <0>; /* -420ps */
57 			txd2-skew-ps = <0>; /* -420ps */
58 			txd3-skew-ps = <0>; /* -420ps */
59 			rxd0-skew-ps = <420>; /* 0ps */
60 			rxd1-skew-ps = <420>; /* 0ps */
61 			rxd2-skew-ps = <420>; /* 0ps */
62 			rxd3-skew-ps = <420>; /* 0ps */
63 			txen-skew-ps = <0>; /* -420ps */
64 			txc-skew-ps = <900>; /* 0ps */
65 			rxdv-skew-ps = <420>; /* 0ps */
66 			rxc-skew-ps = <1680>; /* 780ps */
73 	cap-sd-highspeed;
74 	broken-cd;
75 	bus-width = <4>;
76 	clk-phase-sd-hs = <0>, <135>;
80 	clock-frequency = <25000000>;
86 		#address-cells = <1>;
87 		#size-cells = <1>;
88 		compatible = "micron,mt25qu02g", "jedec,spi-nor";
90 		spi-max-frequency = <100000000>;
92 		m25p,fast-read;
93 		cdns,read-delay = <2>;
94 		cdns,tshsl-ns = <50>;
95 		cdns,tsd2d-ns = <50>;
96 		cdns,tchsh-ns = <4>;
97 		cdns,tslch-ns = <4>;
100 			compatible = "fixed-partitions";
101 			#address-cells = <1>;
102 			#size-cells = <1>;
110 				label = "Root Filesystem - JFFS2";
123 	disable-over-current;