dts/intel/socfpga_agilex_socdk.dts

1 // SPDX-License-Identifier:     GPL-2.0
9 	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 		stdout-path = "serial0:115200n8";
23 		compatible = "gpio-leds";
53 	phy-mode = "rgmii";
54 	phy-handle = <&phy0>;
56 	max-frame-size = <9000>;
59 		#address-cells = <1>;
60 		#size-cells = <0>;
61 		compatible = "snps,dwmac-mdio";
62 		phy0: ethernet-phy@0 {
65 			txd0-skew-ps = <0>; /* -420ps */
66 			txd1-skew-ps = <0>; /* -420ps */
67 			txd2-skew-ps = <0>; /* -420ps */
68 			txd3-skew-ps = <0>; /* -420ps */
69 			rxd0-skew-ps = <420>; /* 0ps */
70 			rxd1-skew-ps = <420>; /* 0ps */
71 			rxd2-skew-ps = <420>; /* 0ps */
72 			rxd3-skew-ps = <420>; /* 0ps */
73 			txen-skew-ps = <0>; /* -420ps */
74 			txc-skew-ps = <900>; /* 0ps */
75 			rxdv-skew-ps = <420>; /* 0ps */
76 			rxc-skew-ps = <1680>; /* 780ps */
83 	cap-sd-highspeed;
84 	broken-cd;
85 	bus-width = <4>;
86 	clk-phase-sd-hs = <0>, <135>;
90 	clock-frequency = <25000000>;
99 	disable-over-current;
109 		#address-cells = <1>;
110 		#size-cells = <1>;
111 		compatible = "micron,mt25qu02g", "jedec,spi-nor";
113 		spi-max-frequency = <100000000>;
115 		m25p,fast-read;
116 		cdns,read-delay = <2>;
117 		cdns,tshsl-ns = <50>;
118 		cdns,tsd2d-ns = <50>;
119 		cdns,tchsh-ns = <4>;
120 		cdns,tslch-ns = <4>;
123 			compatible = "fixed-partitions";
124 			#address-cells = <1>;
125 			#size-cells = <1>;
133 				label = "Root Filesystem - UBIFS";