dts/freescale/s32g2.dtsi

1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6  * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 	interrupt-parent = <&gic>;
14 	#address-cells = <2>;
15 	#size-cells = <2>;
18 		#address-cells = <1>;
19 		#size-cells = <0>;
23 			compatible = "arm,cortex-a53";
25 			enable-method = "psci";
26 			next-level-cache = <&cluster0_l2>;
31 			compatible = "arm,cortex-a53";
33 			enable-method = "psci";
34 			next-level-cache = <&cluster0_l2>;
39 			compatible = "arm,cortex-a53";
41 			enable-method = "psci";
42 			next-level-cache = <&cluster1_l2>;
47 			compatible = "arm,cortex-a53";
49 			enable-method = "psci";
50 			next-level-cache = <&cluster1_l2>;
53 		cluster0_l2: l2-cache0 {
55 			cache-level = <2>;
56 			cache-unified;
59 		cluster1_l2: l2-cache1 {
61 			cache-level = <2>;
62 			cache-unified;
67 		compatible = "arm,cortex-a53-pmu";
72 		compatible = "arm,armv8-timer";
81 			compatible = "arm,psci-1.0";
87 		compatible = "simple-bus";
88 		#address-cells = <1>;
89 		#size-cells = <1>;
93 			compatible = "nxp,s32g2-linflexuart",
94 				     "fsl,s32v234-linflexuart";
101 			compatible = "nxp,s32g2-linflexuart",
102 				     "fsl,s32v234-linflexuart";
109 			compatible = "nxp,s32g2-linflexuart",
110 				     "fsl,s32v234-linflexuart";
116 		gic: interrupt-controller@50800000 {
117 			compatible = "arm,gic-v3";
124 			interrupt-controller;
125 			#interrupt-cells = <3>;