dts/freescale/imx8-ss-dma.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 dma_ipg_clk: clock-dma-ipg {
11 	compatible = "fixed-clock";
12 	#clock-cells = <0>;
13 	clock-frequency = <120000000>;
14 	clock-output-names = "dma_ipg_clk";
18 	compatible = "simple-bus";
19 	#address-cells = <1>;
20 	#size-cells = <1>;
24 		compatible = "fsl,imx7ulp-spi";
26 		#address-cells = <1>;
27 		#size-cells = <0>;
29 		interrupt-parent = <&gic>;
32 		clock-names = "per", "ipg";
33 		assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
34 		assigned-clock-rates = <60000000>;
35 		power-domains = <&pd IMX_SC_R_SPI_0>;
40 		compatible = "fsl,imx7ulp-spi";
42 		#address-cells = <1>;
43 		#size-cells = <0>;
45 		interrupt-parent = <&gic>;
48 		clock-names = "per", "ipg";
49 		assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
50 		assigned-clock-rates = <60000000>;
51 		power-domains = <&pd IMX_SC_R_SPI_1>;
56 		compatible = "fsl,imx7ulp-spi";
58 		#address-cells = <1>;
59 		#size-cells = <0>;
61 		interrupt-parent = <&gic>;
64 		clock-names = "per", "ipg";
65 		assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
66 		assigned-clock-rates = <60000000>;
67 		power-domains = <&pd IMX_SC_R_SPI_2>;
72 		compatible = "fsl,imx7ulp-spi";
74 		#address-cells = <1>;
75 		#size-cells = <0>;
77 		interrupt-parent = <&gic>;
80 		clock-names = "per", "ipg";
81 		assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
82 		assigned-clock-rates = <60000000>;
83 		power-domains = <&pd IMX_SC_R_SPI_3>;
92 		clock-names = "ipg", "baud";
93 		assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
94 		assigned-clock-rates = <80000000>;
95 		power-domains = <&pd IMX_SC_R_UART_0>;
96 		dma-names = "tx","rx";
106 		clock-names = "ipg", "baud";
107 		assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
108 		assigned-clock-rates = <80000000>;
109 		power-domains = <&pd IMX_SC_R_UART_1>;
110 		dma-names = "tx","rx";
120 		clock-names = "ipg", "baud";
121 		assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
122 		assigned-clock-rates = <80000000>;
123 		power-domains = <&pd IMX_SC_R_UART_2>;
124 		dma-names = "tx","rx";
134 		clock-names = "ipg", "baud";
135 		assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
136 		assigned-clock-rates = <80000000>;
137 		power-domains = <&pd IMX_SC_R_UART_3>;
138 		dma-names = "tx","rx";
144 		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
149 		clock-names = "ipg", "per";
150 		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
151 		assigned-clock-rates = <24000000>;
152 		#pwm-cells = <3>;
153 		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
156 	edma2: dma-controller@5a1f0000 {
157 		compatible = "fsl,imx8qm-edma";
159 		#dma-cells = <3>;
160 		dma-channels = <16>;
177 		power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
195 	edma3: dma-controller@5a9f0000 {
196 		compatible = "fsl,imx8qm-edma";
198 		#dma-cells = <3>;
199 		dma-channels = <8>;
208 		power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
218 	spi0_lpcg: clock-controller@5a400000 {
219 		compatible = "fsl,imx8qxp-lpcg";
221 		#clock-cells = <1>;
224 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
225 		clock-output-names = "spi0_lpcg_clk",
227 		power-domains = <&pd IMX_SC_R_SPI_0>;
230 	spi1_lpcg: clock-controller@5a410000 {
231 		compatible = "fsl,imx8qxp-lpcg";
233 		#clock-cells = <1>;
236 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
237 		clock-output-names = "spi1_lpcg_clk",
239 		power-domains = <&pd IMX_SC_R_SPI_1>;
242 	spi2_lpcg: clock-controller@5a420000 {
243 		compatible = "fsl,imx8qxp-lpcg";
245 		#clock-cells = <1>;
248 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
249 		clock-output-names = "spi2_lpcg_clk",
251 		power-domains = <&pd IMX_SC_R_SPI_2>;
254 	spi3_lpcg: clock-controller@5a430000 {
255 		compatible = "fsl,imx8qxp-lpcg";
257 		#clock-cells = <1>;
260 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
261 		clock-output-names = "spi3_lpcg_clk",
263 		power-domains = <&pd IMX_SC_R_SPI_3>;
266 	uart0_lpcg: clock-controller@5a460000 {
267 		compatible = "fsl,imx8qxp-lpcg";
269 		#clock-cells = <1>;
272 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
273 		clock-output-names = "uart0_lpcg_baud_clk",
275 		power-domains = <&pd IMX_SC_R_UART_0>;
278 	uart1_lpcg: clock-controller@5a470000 {
279 		compatible = "fsl,imx8qxp-lpcg";
281 		#clock-cells = <1>;
284 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
285 		clock-output-names = "uart1_lpcg_baud_clk",
287 		power-domains = <&pd IMX_SC_R_UART_1>;
290 	uart2_lpcg: clock-controller@5a480000 {
291 		compatible = "fsl,imx8qxp-lpcg";
293 		#clock-cells = <1>;
296 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
297 		clock-output-names = "uart2_lpcg_baud_clk",
299 		power-domains = <&pd IMX_SC_R_UART_2>;
302 	uart3_lpcg: clock-controller@5a490000 {
303 		compatible = "fsl,imx8qxp-lpcg";
305 		#clock-cells = <1>;
308 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
309 		clock-output-names = "uart3_lpcg_baud_clk",
311 		power-domains = <&pd IMX_SC_R_UART_3>;
314 	adma_pwm_lpcg: clock-controller@5a590000 {
315 		compatible = "fsl,imx8qxp-lpcg";
317 		#clock-cells = <1>;
320 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
321 		clock-output-names = "adma_pwm_lpcg_clk",
323 		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
331 		clock-names = "per", "ipg";
332 		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
333 		assigned-clock-rates = <24000000>;
334 		power-domains = <&pd IMX_SC_R_I2C_0>;
343 		clock-names = "per", "ipg";
344 		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
345 		assigned-clock-rates = <24000000>;
346 		power-domains = <&pd IMX_SC_R_I2C_1>;
355 		clock-names = "per", "ipg";
356 		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
357 		assigned-clock-rates = <24000000>;
358 		power-domains = <&pd IMX_SC_R_I2C_2>;
367 		clock-names = "per", "ipg";
368 		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
369 		assigned-clock-rates = <24000000>;
370 		power-domains = <&pd IMX_SC_R_I2C_3>;
375 		compatible = "nxp,imx8qxp-adc";
376 		#io-channel-cells = <1>;
379 		interrupt-parent = <&gic>;
382 		clock-names = "per", "ipg";
383 		assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
384 		assigned-clock-rates = <24000000>;
385 		power-domains = <&pd IMX_SC_R_ADC_0>;
390 		compatible = "nxp,imx8qxp-adc";
391 		#io-channel-cells = <1>;
394 		interrupt-parent = <&gic>;
397 		clock-names = "per", "ipg";
398 		assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
399 		assigned-clock-rates = <24000000>;
400 		power-domains = <&pd IMX_SC_R_ADC_1>;
405 		compatible = "fsl,imx8qm-flexcan";
408 		interrupt-parent = <&gic>;
411 		clock-names = "ipg", "per";
412 		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
413 		assigned-clock-rates = <40000000>;
414 		power-domains = <&pd IMX_SC_R_CAN_0>;
416 		fsl,clk-source = /bits/ 8 <0>;
417 		fsl,scu-index = /bits/ 8 <0>;
422 		compatible = "fsl,imx8qm-flexcan";
425 		interrupt-parent = <&gic>;
426 		/* CAN0 clock and PD is shared among all CAN instances as
427 		 * CAN1 shares CAN0's clock and to enable CAN0's clock it
432 		clock-names = "ipg", "per";
433 		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
434 		assigned-clock-rates = <40000000>;
435 		power-domains = <&pd IMX_SC_R_CAN_1>;
437 		fsl,clk-source = /bits/ 8 <0>;
438 		fsl,scu-index = /bits/ 8 <1>;
443 		compatible = "fsl,imx8qm-flexcan";
446 		interrupt-parent = <&gic>;
447 		/* CAN0 clock and PD is shared among all CAN instances as
448 		 * CAN2 shares CAN0's clock and to enable CAN0's clock it
453 		clock-names = "ipg", "per";
454 		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
455 		assigned-clock-rates = <40000000>;
456 		power-domains = <&pd IMX_SC_R_CAN_2>;
458 		fsl,clk-source = /bits/ 8 <0>;
459 		fsl,scu-index = /bits/ 8 <2>;
463 	i2c0_lpcg: clock-controller@5ac00000 {
464 		compatible = "fsl,imx8qxp-lpcg";
466 		#clock-cells = <1>;
469 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
470 		clock-output-names = "i2c0_lpcg_clk",
472 		power-domains = <&pd IMX_SC_R_I2C_0>;
475 	i2c1_lpcg: clock-controller@5ac10000 {
476 		compatible = "fsl,imx8qxp-lpcg";
478 		#clock-cells = <1>;
481 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
482 		clock-output-names = "i2c1_lpcg_clk",
484 		power-domains = <&pd IMX_SC_R_I2C_1>;
487 	i2c2_lpcg: clock-controller@5ac20000 {
488 		compatible = "fsl,imx8qxp-lpcg";
490 		#clock-cells = <1>;
493 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
494 		clock-output-names = "i2c2_lpcg_clk",
496 		power-domains = <&pd IMX_SC_R_I2C_2>;
499 	i2c3_lpcg: clock-controller@5ac30000 {
500 		compatible = "fsl,imx8qxp-lpcg";
502 		#clock-cells = <1>;
505 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
506 		clock-output-names = "i2c3_lpcg_clk",
508 		power-domains = <&pd IMX_SC_R_I2C_3>;
511 	adc0_lpcg: clock-controller@5ac80000 {
512 		compatible = "fsl,imx8qxp-lpcg";
514 		#clock-cells = <1>;
517 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
518 		clock-output-names = "adc0_lpcg_clk",
520 		power-domains = <&pd IMX_SC_R_ADC_0>;
523 	adc1_lpcg: clock-controller@5ac90000 {
524 		compatible = "fsl,imx8qxp-lpcg";
526 		#clock-cells = <1>;
529 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
530 		clock-output-names = "adc1_lpcg_clk",
532 		power-domains = <&pd IMX_SC_R_ADC_1>;
535 	can0_lpcg: clock-controller@5acd0000 {
536 		compatible = "fsl,imx8qxp-lpcg";
538 		#clock-cells = <1>;
541 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
542 		clock-output-names = "can0_lpcg_pe_clk",
545 		power-domains = <&pd IMX_SC_R_CAN_0>;