exynos/google/gs101.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2019-2023 Google LLC
6  * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include <dt-bindings/clock/google,gs101.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 	#address-cells = <2>;
17 	#size-cells = <1>;
19 	interrupt-parent = <&gic>;
33 		#address-cells = <1>;
34 		#size-cells = <0>;
36 		cpu-map {
71 		cpu0: cpu@0 {
73 			compatible = "arm,cortex-a55";
74 			reg = <0x0000>;
75 			enable-method = "psci";
76 			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
77 			capacity-dmips-mhz = <250>;
78 			dynamic-power-coefficient = <70>;
83 			compatible = "arm,cortex-a55";
84 			reg = <0x0100>;
85 			enable-method = "psci";
86 			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
87 			capacity-dmips-mhz = <250>;
88 			dynamic-power-coefficient = <70>;
93 			compatible = "arm,cortex-a55";
94 			reg = <0x0200>;
95 			enable-method = "psci";
96 			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
97 			capacity-dmips-mhz = <250>;
98 			dynamic-power-coefficient = <70>;
103 			compatible = "arm,cortex-a55";
104 			reg = <0x0300>;
105 			enable-method = "psci";
106 			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
107 			capacity-dmips-mhz = <250>;
108 			dynamic-power-coefficient = <70>;
113 			compatible = "arm,cortex-a76";
114 			reg = <0x0400>;
115 			enable-method = "psci";
116 			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
117 			capacity-dmips-mhz = <620>;
118 			dynamic-power-coefficient = <284>;
123 			compatible = "arm,cortex-a76";
124 			reg = <0x0500>;
125 			enable-method = "psci";
126 			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
127 			capacity-dmips-mhz = <620>;
128 			dynamic-power-coefficient = <284>;
133 			compatible = "arm,cortex-x1";
134 			reg = <0x0600>;
135 			enable-method = "psci";
136 			cpu-idle-states =  <&HERA_CPU_SLEEP>;
137 			capacity-dmips-mhz = <1024>;
138 			dynamic-power-coefficient = <650>;
143 			compatible = "arm,cortex-x1";
144 			reg = <0x0700>;
145 			enable-method = "psci";
146 			cpu-idle-states =  <&HERA_CPU_SLEEP>;
147 			capacity-dmips-mhz = <1024>;
148 			dynamic-power-coefficient = <650>;
151 		idle-states {
152 			entry-method = "psci";
154 			ANANKE_CPU_SLEEP: cpu-ananke-sleep {
155 				idle-state-name = "c2";
156 				compatible = "arm,idle-state";
157 				arm,psci-suspend-param = <0x0010000>;
158 				entry-latency-us = <70>;
159 				exit-latency-us = <160>;
160 				min-residency-us = <2000>;
163 			ENYO_CPU_SLEEP: cpu-enyo-sleep {
164 				idle-state-name = "c2";
165 				compatible = "arm,idle-state";
166 				arm,psci-suspend-param = <0x0010000>;
167 				entry-latency-us = <150>;
168 				exit-latency-us = <190>;
169 				min-residency-us = <2500>;
172 			HERA_CPU_SLEEP: cpu-hera-sleep {
173 				idle-state-name = "c2";
174 				compatible = "arm,idle-state";
175 				arm,psci-suspend-param = <0x0010000>;
176 				entry-latency-us = <235>;
177 				exit-latency-us = <220>;
178 				min-residency-us = <3500>;
184 	dummy_clk: clock-3 {
185 		compatible = "fixed-clock";
186 		#clock-cells = <0>;
187 		clock-frequency = <12345>;
188 		clock-output-names = "pclk";
195 	ext_24_5m: clock-1 {
196 		compatible = "fixed-clock";
197 		#clock-cells = <0>;
198 		clock-output-names = "oscclk";
201 	ext_200m: clock-2 {
202 		compatible = "fixed-clock";
203 		#clock-cells = <0>;
204 		clock-output-names = "ext-200m";
207 	pmu-0 {
208 		compatible = "arm,cortex-a55-pmu";
212 	pmu-1 {
213 		compatible = "arm,cortex-a76-pmu";
217 	pmu-2 {
218 		compatible = "arm,cortex-x1-pmu";
222 	pmu-3 {
223 		compatible = "arm,dsu-pmu";
224 		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
229 	psci {
230 		compatible = "arm,psci-1.0";
234 	reserved_memory: reserved-memory {
235 		#address-cells = <2>;
236 		#size-cells = <1>;
240 			reg = <0x0 0x90200000 0x400000>;
241 			no-map;
244 		tpu_fw_reserved: tpu-fw@93000000 {
245 			reg = <0x0 0x93000000 0x1000000>;
246 			no-map;
250 			reg = <0x0 0x94000000 0x03000000>;
251 			no-map;
255 			reg = <0x0 0xf8800000 0x02000000>;
256 			no-map;
259 		dss_log_reserved: dss-log-reserved@fd3f0000 {
260 			reg = <0x0 0xfd3f0000 0x0000e000>;
261 			no-map;
264 		debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
265 			reg = <0x0 0xfd3fe000 0x00001000>;
266 			no-map;
269 		bldr_log_reserved: bldr-log-reserved@fd800000 {
270 			reg = <0x0 0xfd800000 0x00100000>;
271 			no-map;
274 		bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
275 			reg = <0x0 0xfd900000 0x00002000>;
276 			no-map;
280 	soc: soc@0 {
281 		compatible = "simple-bus";
282 		#address-cells = <1>;
283 		#size-cells = <1>;
284 		ranges = <0x0 0x0 0x0 0x40000000>;
286 		cmu_misc: clock-controller@10010000 {
287 			compatible = "google,gs101-cmu-misc";
288 			reg = <0x10010000 0x8000>;
289 			#clock-cells = <1>;
292 			clock-names = "bus", "sss";
296 			compatible = "google,gs101-wdt";
297 			reg = <0x10060000 0x100>;
298 			interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>;
301 			clock-names = "watchdog", "watchdog_src";
302 			samsung,syscon-phandle = <&pmu_system_controller>;
303 			samsung,cluster-index = <0>;
308 			compatible = "google,gs101-wdt";
309 			reg = <0x10070000 0x100>;
310 			interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>;
313 			clock-names = "watchdog", "watchdog_src";
314 			samsung,syscon-phandle = <&pmu_system_controller>;
315 			samsung,cluster-index = <1>;
319 		gic: interrupt-controller@10400000 {
320 			compatible = "arm,gic-v3";
321 			#interrupt-cells = <4>;
322 			interrupt-controller;
323 			reg = <0x10400000 0x10000>, /* GICD */
324 			      <0x10440000 0x100000>;/* GICR * 8 */
325 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
327 			ppi-partitions {
328 				ppi_cluster0: interrupt-partition-0 {
332 				ppi_cluster1: interrupt-partition-1 {
336 				ppi_cluster2: interrupt-partition-2 {
343 			compatible = "google,gs101-peric0-sysreg", "syscon";
344 			reg = <0x10820000 0x10000>;
348 			compatible = "google,gs101-pinctrl";
349 			reg = <0x10840000 0x00001000>;
350 			interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
354 			compatible = "google,gs101-usi",
355 				     "samsung,exynos850-usi";
356 			reg = <0x10a000c0 0x20>;
358 			#address-cells = <1>;
359 			#size-cells = <1>;
361 			clock-names = "pclk", "ipclk";
362 			samsung,sysreg = <&sysreg_peric0 0x1020>;
367 				compatible = "google,gs101-uart";
368 				reg = <0x10a00000 0xc0>;
369 				reg-io-width = <4>;
371 					      IRQ_TYPE_LEVEL_HIGH 0>;
372 				clocks = <&dummy_clk 0>, <&dummy_clk 0>;
373 				clock-names = "uart", "clk_uart_baud0";
374 				samsung,uart-fifosize = <256>;
380 			compatible = "google,gs101-peric1-sysreg", "syscon";
381 			reg = <0x10c20000 0x10000>;
385 			compatible = "google,gs101-pinctrl";
386 			reg = <0x10c40000 0x00001000>;
387 			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
391 			compatible = "google,gs101-pinctrl";
392 			reg = <0x11840000 0x00001000>;
393 			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
397 			compatible = "google,gs101-pinctrl";
398 			reg = <0x14440000 0x00001000>;
399 			interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
402 		cmu_apm: clock-controller@17400000 {
403 			compatible = "google,gs101-cmu-apm";
404 			reg = <0x17400000 0x8000>;
405 			#clock-cells = <1>;
408 			clock-names = "oscclk";
412 			compatible = "google,gs101-apm-sysreg", "syscon";
413 			reg = <0x174204e0 0x1000>;
416 		pmu_system_controller: system-controller@17460000 {
417 			compatible = "google,gs101-pmu", "syscon";
418 			reg = <0x17460000 0x10000>;
422 			compatible = "google,gs101-pinctrl";
423 			reg = <0x174d0000 0x00001000>;
425 			wakeup-interrupt-controller {
426 				compatible = "google,gs101-wakeup-eint",
427 					     "samsung,exynos850-wakeup-eint",
428 					     "samsung,exynos7-wakeup-eint";
433 			compatible = "google,gs101-pinctrl";
434 			reg = <0x174e0000 0x00001000>;
436 			wakeup-interrupt-controller {
437 				compatible = "google,gs101-wakeup-eint",
438 					     "samsung,exynos850-wakeup-eint",
439 					     "samsung,exynos7-wakeup-eint";
444 			compatible = "google,gs101-pinctrl";
445 			reg = <0x17940000 0x00001000>;
449 			compatible = "google,gs101-pinctrl";
450 			reg = <0x17a80000 0x00001000>;
453 		cmu_top: clock-controller@1e080000 {
454 			compatible = "google,gs101-cmu-top";
455 			reg = <0x1e080000 0x8000>;
456 			#clock-cells = <1>;
459 			clock-names = "oscclk";
464 		compatible = "arm,armv8-timer";
466 		   <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
467 		   <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
468 		   <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
469 		   <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
473 #include "gs101-pinctrl.dtsi"