Lines Matching +full:spin +full:- +full:table
1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
43 enable-method = "spin-table";
44 cpu-release-addr = <0x0 0x8000fff8>;
45 next-level-cache = <&L2_0>;
51 enable-method = "spin-table";
52 cpu-release-addr = <0x0 0x8000fff8>;
53 next-level-cache = <&L2_0>;
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x8000fff8>;
61 next-level-cache = <&L2_0>;
67 enable-method = "spin-table";
68 cpu-release-addr = <0x0 0x8000fff8>;
69 next-level-cache = <&L2_0>;
72 L2_0: l2-cache0 {
74 cache-level = <2>;
75 cache-unified;
85 reserved-memory {
86 #address-cells = <2>;
87 #size-cells = <2>;
93 compatible = "shared-dma-pool";
95 no-map;
99 gic: interrupt-controller@2c001000 {
100 compatible = "arm,gic-400", "arm,cortex-a15-gic";
101 #interrupt-cells = <3>;
102 #address-cells = <0>;
103 interrupt-controller;
112 compatible = "arm,armv8-timer";
117 clock-frequency = <100000000>;
121 compatible = "arm,armv8-pmuv3";
129 compatible = "arm,rtsm-display";
132 remote-endpoint = <&clcd_pads>;
138 #interrupt-cells = <1>;
139 interrupt-map-mask = <0 0 63>;
140 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,