Lines Matching +full:trace +full:- +full:buffer +full:- +full:extension
1 # SPDX-License-Identifier: GPL-2.0-only
196 if $(cc-option,-fpatchable-function-entry=2)
261 ARM 64-bit (AArch64) Linux support.
271 depends on $(cc-option,-fpatchable-function-entry=2)
304 # VA_BITS - PAGE_SHIFT - 3
380 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
435 at stage-2.
443 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
448 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
451 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
457 data cache clean-and-invalidate.
465 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
470 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
479 data cache clean-and-invalidate.
487 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
492 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
495 If a Cortex-A53 processor is executing a store or prefetch for
502 data cache clean-and-invalidate.
510 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
515 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
524 data cache clean-and-invalidate.
532 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
536 erratum 832075 on Cortex-A57 parts up to r1p2.
538 Affected Cortex-A57 parts might deadlock when exclusive load/store
539 instructions to Write-Back memory are mixed with Device loads.
541 The workaround is to promote device loads to use Load-Acquire
550 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
555 erratum 834220 on Cortex-A57 parts up to r1p2.
557 Affected Cortex-A57 parts might report a Stage 2 translation
571 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
575 This option removes the AES hwcap for aarch32 user-space to
576 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
587 bool "Cortex-A53: 845719: a load might read incorrect data"
592 erratum 845719 on Cortex-A53 parts up to r0p4.
594 When running a compat (AArch32) userspace on an affected Cortex-A53
600 return to a 32-bit task.
608 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
611 This option links the kernel with '--fix-cortex-a53-843419' and
614 Cortex-A53 parts up to r0p4.
619 def_bool $(ld-option,--fix-cortex-a53-843419)
622 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
625 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
627 Affected Cortex-A55 cores (all revisions) could cause incorrect
629 without a break-before-make. The workaround is to disable the usage
636 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
640 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
643 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
653 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
657 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
659 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
666 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
670 This option adds work arounds for ARM Cortex-A57 erratum 1319537
673 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
679 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
683 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
685 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
695 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
699 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
701 Under very rare circumstances, affected Cortex-A55 CPUs
702 may not handle a race between a break-before-make sequence on one
712 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
716 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
718 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
722 break-before-make sequence, then under very rare circumstances
728 bool "Cortex-A76: Software Step might prevent interrupt recognition"
731 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
733 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
746 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
749 This option adds a workaround for ARM Neoverse-N1 erratum
752 Affected Neoverse-N1 cores could execute a stale instruction when
757 forces user-space to perform cache maintenance.
762 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
765 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
767 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
768 of a store-exclusive or read of PAR_EL1 and a load with device or
769 non-cacheable memory attributes. The workaround depends on a firmware
785 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
788 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
789 Affected Cortex-A510 might not respect the ordering rules for
796 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
799 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
800 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
808 previous guest entry, and can be restored from the in-memory copy.
813 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
816 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
817 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
821 user-space should not be using these instructions.
826 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
831 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
833 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
834 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
838 256 bytes before enabling the buffer and filling the first 256 bytes of
839 the buffer with ETM ignore packets upon disabling.
844 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
849 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
851 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
852 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
856 256 bytes before enabling the buffer and filling the first 256 bytes of
857 the buffer with ETM ignore packets upon disabling.
865 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
869 Enable workaround for ARM Cortex-A710 erratum 2054223
871 Affected cores may fail to flush the trace data on a TSB instruction, when
872 the PE is in trace prohibited state. This will cause losing a few bytes
873 of the trace cached.
880 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
884 Enable workaround for ARM Neoverse-N2 erratum 2067961
886 Affected cores may fail to flush the trace data on a TSB instruction, when
887 the PE is in trace prohibited state. This will cause losing a few bytes
888 of the trace cached.
898 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
903 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
905 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
916 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
921 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
923 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
934 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
938 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
940 Under very rare circumstances, affected Cortex-A510 CPUs
941 may not handle a race between a break-before-make sequence on one
951 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
955 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
957 Affected Cortex-A510 core might fail to write into system registers after the
969 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
973 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
975 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
976 prohibited within the CPU. As a result, the trace buffer or trace buffer state
977 might be corrupted. This happens after TRBE buffer has been enabled by setting
979 execution changes from a context, in which trace is prohibited to one where it
980 isn't, or vice versa. In these mentioned conditions, the view of whether trace
981 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
982 the trace buffer state might be corrupted.
985 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
992 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
996 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
998 Affected Cortex-A510 core might cause trace data corruption, when being written
1000 trace data.
1010 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1014 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1017 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1027 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1030 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1032 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1033 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1036 Only user-space does executable to non-executable permission transition via
1037 mprotect() system call. Workaround the problem by doing a break-before-make
1046 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1050 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1052 On an affected Cortex-A520 core, a speculatively executed unprivileged
1060 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1064 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1066 On an affected Cortex-A510 core, a speculatively executed unprivileged
1079 This implements two gicv3-its errata workarounds for ThunderX. Both
1119 contains data for a non-current ASID. The fix is to
1130 interrupts in host. Trapping both GICv3 group-0 and group-1
1153 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1156 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1157 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1161 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1162 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1163 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1164 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1167 The workaround only affects the Fujitsu-A64FX.
1227 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1237 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1244 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1248 MSI doorbell writes with non-zero values for the device ID.
1277 look-up. AArch32 emulation requires applications compiled
1293 bool "36-bit" if EXPERT
1297 bool "39-bit"
1301 bool "42-bit"
1305 bool "47-bit"
1309 bool "48-bit"
1312 bool "52-bit"
1315 Enable 52-bit virtual addressing for userspace when explicitly
1316 requested via a hint to mmap(). The kernel will also use 52-bit
1318 this feature is available, otherwise it reverts to 48-bit).
1320 NOTE: Enabling 52-bit virtual addressing in conjunction with
1323 impact on its susceptibility to brute-force attacks.
1325 If unsure, select 48-bit virtual addressing instead.
1330 bool "Force 52-bit virtual addresses for userspace"
1333 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1334 to maintain compatibility with older software by providing 48-bit VAs
1337 This configuration option disables the 48-bit compatibility logic, and
1338 forces all userspace addresses to be 52-bit on HW that supports it. One
1359 bool "48-bit"
1362 bool "52-bit (ARMv8.2)"
1366 Enable support for a 52-bit physical address space, introduced as
1367 part of the ARMv8.2-LPA extension.
1370 do not support ARMv8.2-LPA, but with some added memory overhead (and
1389 bool "Build big-endian kernel"
1391 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1394 Say Y if you plan on running a kernel with a big-endian userspace.
1397 bool "Build little-endian kernel"
1399 Say Y if you plan on running a kernel with a little-endian userspace.
1405 bool "Multi-core scheduler support"
1407 Multi-core scheduler support improves the CPU scheduler's decision
1408 making when dealing with multi-core CPU chips at a cost of slightly
1417 by sharing mid-level caches, last-level cache tags or internal
1428 int "Maximum number of CPUs (2-4096)"
1433 bool "Support for hot-pluggable CPUs"
1450 Enable NUMA (Non-Uniform Memory Access) support.
1478 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1544 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1547 # ----+-------------------+--------------+----------------------+-------------------------+
1575 Speculation attacks against some high-performance processors can
1587 Speculation attacks against some high-performance processors can
1589 When taking an exception from user-space, a sequence of branches
1596 Apply read-only attributes of VM areas to the linear alias of
1597 the backing pages as well. This prevents code or read-only data
1610 user-space memory directly by pointing TTBR0_EL1 to a reserved
1621 Documentation/arch/arm64/tagged-address-abi.rst.
1624 bool "Kernel support for 32-bit EL0"
1630 This option enables support for a 32-bit EL0 running under a 64-bit
1631 kernel at EL1. AArch32-specific components such as system calls,
1639 If you want to execute 32-bit userspace applications, say Y.
1644 bool "Enable kuser helpers page for 32-bit applications"
1647 Warning: disabling this option may break 32-bit user programs.
1671 bool "Enable vDSO for 32-bit applications"
1677 Place in the process address space of 32-bit applications an
1681 You must have a 32-bit build of glibc 2.22 or later for programs
1685 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1689 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1690 otherwise with '-marm'.
1693 bool "Fix up misaligned multi-word loads and stores in user space"
1735 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1736 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1751 The SETEND instruction alters the data-endianness of the
1759 for this feature to be enabled. If a new CPU - which doesn't support mixed
1760 endian - is hotplugged in after this feature has been enabled, there could
1779 Similarly, writes to read-only pages with the DBM bit set will
1780 clear the read-only bit (AP[2]) instead of raising a
1784 to work on pre-ARMv8.1 hardware and the performance impact is
1792 prevents the kernel or hypervisor from accessing user-space (EL0)
1802 def_bool $(as-instr,.arch_extension lse)
1817 Say Y here to make use of these instructions for the in-kernel
1828 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1831 def_bool $(as-instr,.arch armv8.2-a+sha3)
1858 and access the new registers if the system supports the extension.
1891 context-switched along with the process.
1914 If the compiler supports the -mbranch-protection or
1915 -msign-return-address flag (e.g. GCC 7 or later), then this option
1926 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1930 def_bool $(cc-option,-msign-return-address=all)
1933 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1936 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1939 def_bool $(as-instr,.arch_extension rcpc)
1946 bool "Enable support for the Activity Monitors Unit CPU extension"
1949 The activity monitors extension is an optional extension introduced
1953 To enable the use of this extension on CPUs that implement it, say Y.
1957 extension. The required support is present in:
1969 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1976 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1987 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2021 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2032 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2048 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2052 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2055 bool "Memory Tagging Extension support"
2067 architectural support for run-time, always-on detection of
2069 to eliminate vulnerabilities arising from memory-unsafe
2073 Extension at EL0 (i.e. for userspace).
2077 not be allowed a late bring-up.
2083 Documentation/arch/arm64/memory-tagging-extension.rst.
2095 Access Never to be used with Execute-only mappings.
2102 bool "ARM Scalable Vector Extension support"
2105 The Scalable Vector Extension (SVE) is an extension to the AArch64
2110 To enable use of this extension on CPUs that implement it, say Y.
2126 If you need the kernel to boot on SVE-capable hardware with broken
2133 bool "ARM Scalable Matrix Extension support"
2137 The Scalable Matrix Extension (SME) is an extension to the AArch64
2144 bool "Support for NMI-like interrupts"
2147 Adds support for mimicking Non-Maskable Interrupts through the use of
2190 random u64 value in /chosen/kaslr-seed at kernel entry.
2217 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2249 Provide a set of default command-line options at build time by
2263 Uses the command-line options passed by the boot loader. If
2273 command-line options your boot loader passes to the kernel.
2295 by UEFI firmware (such as non-volatile variables, realtime
2309 continue to boot on existing non-UEFI platforms.