Lines Matching +full:0 +full:x3f000000

37 	mrc	p15, 0, r0, c1, c0, 0
38 	bic	r0, r0, #0x3f000000		@ bank/f/lock/s
39 	bic	r0, r0, #0x0000000c		@ w-buffer/cache
40 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
50 	mov	ip, #0
51 	mcr	p15, 0, ip, c7, c0, 0		@ invalidate cache
52 	mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
53 	bic	ip, ip, #0x0000000c		@ ............wc..
54 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
61 	mov	r0, #0
62 	mcr	p15, 0, r0, c7, c0, 0		@ invalidate caches
64 	mcr	p15, 0, r0, c6, c3		@ disable area 3~7
65 	mcr	p15, 0, r0, c6, c4
66 	mcr	p15, 0, r0, c6, c5
67 	mcr	p15, 0, r0, c6, c6
68 	mcr	p15, 0, r0, c6, c7
70 	mov	r0, #0x0000003F			@ base = 0, size = 4GB
71 	mcr	p15, 0, r0, c6,	c0		@ set area 0, default
73 	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
81 	mcr	p15, 0, r0, c6,	c1		@ set area 1, RAM
83 	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
85 	cmp	r3, #0
86 	moveq	r0, #0
94 2:	mcr	p15, 0, r0, c6,	c2		@ set area 2, ROM/FLASH
96 	mov	r0, #0x06
97 	mcr	p15, 0, r0, c2, c0		@ Region 1&2 cacheable
99 	mov	r0, #0x00			@ disable whole write buffer
101 	mov	r0, #0x02			@ Region 1 write bufferred
103 	mcr	p15, 0, r0, c3, c0
105 	mov	r0, #0x10000
106 	sub	r0, r0, #1			@ r0 = 0xffff
107 	mcr	p15, 0, r0, c5, c0		@ all read/write access
109 	mrc	p15, 0, r0, c1, c0		@ get control register
110 	bic	r0, r0, #0x3F000000		@ set to standard caching mode
112 	orr	r0, r0, #0x0000000d		@ MPU/Cache/WB
134 	.long	0x41807400
135 	.long	0xfffffff0
136 	.long	0
137 	.long	0
144 	.long	0
145 	.long	0