arm/mm/cache-v6.S

34  *	r0 - set to 0
38 	mov	r0, #0
42 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
43 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
44 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
45 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
51 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I-cache
64 	mov	r0, #0
66 	mcr	p15, 0, r0, c7, c14, 0		@ D cache clean+invalidate
68 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
73 	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
134 	bic	r0, r0, #CACHE_LINE_SIZE - 1
136  USER(	mcr	p15, 0, r0, c7, c10, 1	)	@ clean D line
137 	add	r0, r0, #CACHE_LINE_SIZE
138 	cmp	r0, r1
141 	mov	r0, #0
143 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
145 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
150 	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
155  * Fault handling for the cache operation above. If the virtual address in r0
159 	mov	r0, #-EFAULT
175 	add	r1, r0, r1
176 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
179 	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
181 	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate unified line
183 	add	r0, r0, #D_CACHE_LINE_SIZE
184 	cmp	r0, r1
187 	mov	r0, #0
188 	mcr	p15, 0, r0, c7, c10, 4
204 	tst	r0, #D_CACHE_LINE_SIZE - 1
205 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
207 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D line
209 	mcrne	p15, 0, r0, c7, c11, 1		@ clean unified line
220 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D line
222 	mcr	p15, 0, r0, c7, c7, 1		@ invalidate unified line
224 	add	r0, r0, #D_CACHE_LINE_SIZE
225 	cmp	r0, r1
227 	mov	r0, #0
228 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
237 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
240 	mcr	p15, 0, r0, c7, c10, 1		@ clean D line
242 	mcr	p15, 0, r0, c7, c11, 1		@ clean unified line
244 	add	r0, r0, #D_CACHE_LINE_SIZE
245 	cmp	r0, r1
247 	mov	r0, #0
248 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
257 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
260 	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
262 	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate line
264 	add	r0, r0, #D_CACHE_LINE_SIZE
265 	cmp	r0, r1
267 	mov	r0, #0
268 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
278 	add	r1, r1, r0
291 	add	r1, r1, r0