Lines Matching +full:0 +full:x260
16 #define REG_SET 0x4
17 #define REG_CLR 0x8
19 #define ANADIG_REG_2P5 0x130
20 #define ANADIG_REG_CORE 0x140
21 #define ANADIG_ANA_MISC0 0x150
22 #define ANADIG_DIGPROG 0x260
23 #define ANADIG_DIGPROG_IMX6SL 0x280
24 #define ANADIG_DIGPROG_IMX7D 0x800
26 #define SRC_SBMR2 0x1c
28 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
29 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
30 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
31 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
33 #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
45 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? in imx_anatop_enable_weak2p5()
104 anatop_base = of_iomap(np, 0); in imx_init_revision_from_anatop()
118 revision = digprog & 0xff; in imx_init_revision_from_anatop()
122 * MINOR: [7: 0], the minor silicon revison; in imx_init_revision_from_anatop()
129 major_part = (digprog >> 8) & 0xf; in imx_init_revision_from_anatop()
130 minor_part = digprog & 0xf; in imx_init_revision_from_anatop()
139 src_base = of_iomap(src_np, 0); in imx_init_revision_from_anatop()
147 digprog &= ~(0xff << 16); in imx_init_revision_from_anatop()
154 mxc_set_cpu_type(digprog >> 16 & 0xff); in imx_init_revision_from_anatop()