arm/kernel/perf_event_v7.c

655 #define	ARMV7_IDX_COUNTER0	1
657 	(ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
660 #define	ARMV7_COUNTER_MASK	(ARMV7_MAX_COUNTERS - 1)
675 #define ARMV7_PMNC_E		(1 << 0) /* Enable all counters */
676 #define ARMV7_PMNC_P		(1 << 1) /* Reset all counters */
677 #define ARMV7_PMNC_C		(1 << 2) /* Cycle counter reset */
678 #define ARMV7_PMNC_D		(1 << 3) /* CCNT counts every 64th cpu cycle */
679 #define ARMV7_PMNC_X		(1 << 4) /* Export to ETM */
680 #define ARMV7_PMNC_DP		(1 << 5) /* Disable CCNT if non-invasive debug*/
707 #define ARMV7_SDER_SUNIDEN	BIT(1) /* Permit non-invasive debug */
712 	asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));  in armv7_pmnc_read()
720 	asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));  in armv7_pmnc_write()
742 	asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));  in armv7_pmnc_select_counter()
787 	asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));  in armv7_pmnc_write_evtsel()
793 	asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));  in armv7_pmnc_enable_counter()
799 	asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));  in armv7_pmnc_disable_counter()
805 	asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));  in armv7_pmnc_enable_intens()
814 	asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));  in armv7_pmnc_disable_intens()
823 	asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));  in armv7_pmnc_getreset_flags()
827 	asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));  in armv7_pmnc_getreset_flags()
840 	asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));  in armv7_pmnc_dump_regs()
843 	asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));  in armv7_pmnc_dump_regs()
846 	asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));  in armv7_pmnc_dump_regs()
849 	asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));  in armv7_pmnc_dump_regs()
852 	asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));  in armv7_pmnc_dump_regs()
864 		asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));  in armv7_pmnc_dump_regs()
1081 		asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val));  in armv7pmu_reset()
1083 		asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val));  in armv7pmu_reset()
1172 	*nb_cnt += 1;  in armv7_read_num_pmnc_events()
1179 				     &arm_pmu->num_events, 1);  in armv7_probe_num_events()
1273  *  PMRESR0   | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 0
1275  *  PMRESR1   | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 1
1277  *  PMRESR2   | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 2
1281  *              EN | G=3  | G=2  | G=1  | G=0
1287  *      N  = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR)
1292  *  Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
1301 #define KRAIT_EVENT		(1 << 16)
1310 #define EVENT_CPU(event)	(!!(event & KRAIT_EVENT))	/* N=1 */
1318 		asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val));  in krait_read_pmresrn()
1320 	case 1:  in krait_read_pmresrn()
1321 		asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val));  in krait_read_pmresrn()
1324 		asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val));  in krait_read_pmresrn()
1337 		asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val));  in krait_write_pmresrn()
1339 	case 1:  in krait_write_pmresrn()
1340 		asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val));  in krait_write_pmresrn()
1343 		asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val));  in krait_write_pmresrn()
1535 	krait_write_pmresrn(1, 0);  in krait_pmu_reset()
1567 	bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1;  in krait_event_to_bit()
1580 	int bit = -1;  in krait_pmu_get_event_idx()
1648  *  LPM0      | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 0
1650  *  LPM1      | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 1
1652  *  LPM2      | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 2
1654  *  L2LPM     | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 3
1658  *              EN | G=3  | G=2  | G=1  | G=0
1665  *      N  = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM)
1670  *  Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2
1687 	case 1:  in scorpion_read_pmresrn()
1688 		asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));  in scorpion_read_pmresrn()
1709 	case 1:  in scorpion_write_pmresrn()
1710 		asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val));  in scorpion_write_pmresrn()
1856 	scorpion_write_pmresrn(1, 0);  in scorpion_pmu_reset()
1888 	bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1;  in scorpion_event_to_bit()
1901 	int bit = -1;  in scorpion_pmu_get_event_idx()