Lines Matching +full:processor +full:- +full:b +full:- +full:side
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
9 * Low-level vector interface routines
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
27 #include <asm/uaccess-asm.h>
29 #include "entry-header.S"
52 b 1f
64 ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC
74 @ Call the processor-specific abort handler:
76 @ r2 - pt_regs
77 @ r4 - aborted context pc
78 @ r5 - aborted context psr
84 ldr_va ip, processor, offset=PROCESSOR_DABT_FUNC
98 ARM( stmib sp, {r1 - lr} )
99 THUMB( stmia sp, {r0 - r12} )
107 b common_invalid
112 b common_invalid
117 b common_invalid
128 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
133 ldmia r0, {r4 - r6}
135 mov r7, #-1 @ "" "" "" ""
137 stmia r0, {r5 - r7} @ lr_<exception>,
141 b bad_mode
161 UNWIND(.save {r0 - pc} )
174 ARM( stmib sp, {r1 - r12} )
175 THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2
177 ldmia r0, {r3 - r5}
179 mov r6, #-1 @ "" "" "" ""
190 @ r2 - sp_svc
191 @ r3 - lr_svc
192 @ r4 - lr_<exception>, already fixed up for correct return/restart
193 @ r5 - spsr_<exception>
194 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
196 stmia r7, {r2 - r6}
245 b 1b
258 b do_undefinstr
324 stmfd sp!, {r1 - r2}
329 ldmfd sp!, {r1 - r2}
346 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
357 ARM( stmib sp, {r1 - r12} )
358 THUMB( stmia sp, {r0 - r12} )
363 ldmia r0, {r3 - r5}
365 mov r6, #-1 @ "" "" "" ""
373 @ r4 - lr_<exception>, already fixed up for correct return/restart
374 @ r5 - spsr_<exception>
375 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
379 stmia r0, {r4 - r6}
381 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
428 b ret_from_exception
439 b ret_to_user_from_irq
465 b ret_from_exception
484 b ret_to_user
509 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
510 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
547 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
550 ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously
565 @ switches us to another stack, with few other side effects. In order
583 @ involving the PC, and decorate them with PC-relative group
594 str sp, [ip, #-4]! @ Preserve original SP value
602 str ip, [sp, #-8]! @ store original SP
641 * Each segment is 32-byte aligned and will be moved to the top of the high
659 .if (. - \sym) & 3
660 .rept 4 - (. - \sym) & 3
664 .rept (\size - (. - \sym)) / 4
692 beq 1b @ if no then retry
723 @ 1b = first critical insn, 2b = last critical insn.
724 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
726 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
728 rsbscs r8, r8, #(2b - 1b)
738 mov r0, #-1
781 @ 1b = first critical insn, 2b = last critical insn.
782 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
784 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
786 rsbscs r8, r8, #(2b - 1b)
793 mov r0, #-1
805 beq 1b
807 /* beware -- each __kuser slot must be 8 instructions max */
808 ALT_SMP(b __kuser_memory_barrier)
816 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
825 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
844 * SP points to a minimal amount of processor-private memory, the address
900 3: W(b) . + 4
902 bne 3b
906 b .Lvec_\name
933 b vector_und
951 .long __irq_invalid @ b
974 .long __dabt_invalid @ b
997 .long __pabt_invalid @ b
1020 .long __und_invalid @ b
1030 *-----------------------------------------------------------------------------
1032 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1036 b vector_addrexcptn
1040 *-----------------------------------------------------------------------------
1059 .long __fiq_svc @ b
1068 W(b) vector_rst
1069 W(b) vector_und
1073 W(b) vector_pabt
1074 W(b) vector_dabt
1075 W(b) vector_addrexcptn
1076 W(b) vector_irq
1077 W(b) vector_fiq
1081 W(b) vector_rst
1082 W(b) vector_bhb_loop8_und
1086 W(b) vector_bhb_loop8_pabt
1087 W(b) vector_bhb_loop8_dabt
1088 W(b) vector_addrexcptn
1089 W(b) vector_bhb_loop8_irq
1090 W(b) vector_bhb_loop8_fiq
1093 W(b) vector_rst
1094 W(b) vector_bhb_bpiall_und
1098 W(b) vector_bhb_bpiall_pabt
1099 W(b) vector_bhb_bpiall_dabt
1100 W(b) vector_addrexcptn
1101 W(b) vector_bhb_bpiall_irq
1102 W(b) vector_bhb_bpiall_fiq