dts/unisoc/rda8810pl.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
13 	interrupt-parent = <&intc>;
14 	#address-cells = <1>;
15 	#size-cells = <1>;
18 		#address-cells = <1>;
19 		#size-cells = <0>;
23 			compatible = "arm,cortex-a5";
24 			reg = <0x0>;
29 		compatible = "mmio-sram";
30 		reg = <0x100000 0x10000>;
31 		#address-cells = <1>;
32 		#size-cells = <1>;
37 		compatible = "simple-bus";
38 		#address-cells = <1>;
39 		#size-cells = <1>;
43 			compatible = "rda,8810pl-gpio";
44 			reg = <0x1a08000 0x1000>;
45 			gpio-controller;
46 			#gpio-cells = <2>;
52 		compatible = "simple-bus";
53 		#address-cells = <1>;
54 		#size-cells = <1>;
57 		intc: interrupt-controller@0 {
58 			compatible = "rda,8810pl-intc";
59 			reg = <0x0 0x1000>;
60 			interrupt-controller;
61 			#interrupt-cells = <2>;
66 		compatible = "simple-bus";
67 		#address-cells = <1>;
68 		#size-cells = <1>;
72 			compatible = "rda,8810pl-timer";
73 			reg = <0x10000 0x1000>;
76 			interrupt-names = "hwtimer", "ostimer";
80 			compatible = "rda,8810pl-gpio";
81 			reg = <0x30000 0x1000>;
82 			gpio-controller;
83 			#gpio-cells = <2>;
85 			interrupt-controller;
86 			#interrupt-cells = <2>;
91 			compatible = "rda,8810pl-gpio";
92 			reg = <0x31000 0x1000>;
93 			gpio-controller;
94 			#gpio-cells = <2>;
96 			interrupt-controller;
97 			#interrupt-cells = <2>;
102 			compatible = "rda,8810pl-gpio";
103 			reg = <0x32000 0x1000>;
104 			gpio-controller;
105 			#gpio-cells = <2>;
107 			interrupt-controller;
108 			#interrupt-cells = <2>;
114 		compatible = "simple-bus";
115 		#address-cells = <1>;
116 		#size-cells = <1>;
120 			compatible = "rda,8810pl-uart";
121 			reg = <0x0 0x1000>;
127 			compatible = "rda,8810pl-uart";
128 			reg = <0x10000 0x1000>;
134 			compatible = "rda,8810pl-uart";
135 			reg = <0x90000 0x1000>;
141 	l2: cache-controller@21100000 {
142 		compatible = "arm,pl310-cache";
143 		reg = <0x21100000 0x1000>;
144 		cache-unified;
145 		cache-level = <2>;