Lines Matching +full:adc +full:- +full:channel +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
14 reg-names = "m_can", "message_ram";
17 interrupt-names = "int0", "int1";
19 clock-names = "hclk", "cclk";
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
27 reg-names = "m_can", "message_ram";
30 interrupt-names = "int0", "int1";
32 clock-names = "hclk", "cclk";
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
37 adc_1: adc@48003000 {
38 compatible = "st,stm32mp13-adc-core";
42 clock-names = "bus", "adc";
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
49 adc1: adc@0 {
50 compatible = "st,stm32mp13-adc";
51 #io-channel-cells = <1>;
52 #address-cells = <1>;
53 #size-cells = <0>;
55 interrupt-parent = <&adc_1>;
58 dma-names = "rx";
61 channel@18 {