dts/st/stm32f746.dtsi

45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
251 			clocks = <&rcc 1 CLK_RTC>;
252 			assigned-clocks = <&rcc 1 CLK_RTC>;
253 			assigned-clock-parents = <&rcc 1 CLK_LSE>;
265 			resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
266 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
274 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
283 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
293 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
301 			clocks = <&rcc 1 CLK_USART2>;
309 			clocks = <&rcc 1 CLK_USART3>;
317 			clocks = <&rcc 1 CLK_UART4>;
325 			clocks = <&rcc 1 CLK_UART5>;
334 			resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
335 			clocks = <&rcc 1 CLK_I2C1>;
346 			resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
347 			clocks = <&rcc 1 CLK_I2C2>;
358 			resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
359 			clocks = <&rcc 1 CLK_I2C3>;
370 			resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
371 			clocks = <&rcc 1 CLK_I2C4>;
382 			resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
383 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
392 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
400 			resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
401 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
411 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
420 			clocks = <&rcc 1 CLK_UART7>;
428 			clocks = <&rcc 1 CLK_UART8>;
437 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
459 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
480 			clocks = <&rcc 1 CLK_USART1>;
488 			clocks = <&rcc 1 CLK_USART6>;
496 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
507 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
520 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
530 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
537 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
553 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
573 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
587 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
604 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
614 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
622 			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
623 			clocks = <&rcc 1 CLK_LCD>;
636 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
640 		rcc: rcc@40023800 {  label
643 			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
647 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
662 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
678 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
688 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
700 			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
708 	clocks = <&rcc 1 0>;