dts/st/stm32f746.dtsi

48 	#address-cells = <1>;
49 	#size-cells = <1>;
79 			#address-cells = <1>;
93 			timer@1 {
95 				reg = <1>;
101 			#address-cells = <1>;
123 			#address-cells = <1>;
144 		timers5: timers@40000c00 {
145 			#address-cells = <1>;
167 			#address-cells = <1>;
183 			#address-cells = <1>;
199 			#address-cells = <1>;
220 		timers13: timers@40001c00 {
251 			clocks = <&rcc 1 CLK_RTC>;
252 			assigned-clocks = <&rcc 1 CLK_RTC>;
253 			assigned-clock-parents = <&rcc 1 CLK_LSE>;
255 			interrupts = <17 1>;
278 			#address-cells = <1>;
287 		spi3: spi@40003c00 {
288 			#address-cells = <1>;
301 			clocks = <&rcc 1 CLK_USART2>;
309 			clocks = <&rcc 1 CLK_USART3>;
313 		usart4: serial@40004c00 {
317 			clocks = <&rcc 1 CLK_UART4>;
325 			clocks = <&rcc 1 CLK_UART5>;
335 			clocks = <&rcc 1 CLK_I2C1>;
336 			#address-cells = <1>;
347 			clocks = <&rcc 1 CLK_I2C2>;
348 			#address-cells = <1>;
353 		i2c3: i2c@40005c00 {
359 			clocks = <&rcc 1 CLK_I2C3>;
360 			#address-cells = <1>;
371 			clocks = <&rcc 1 CLK_I2C4>;
372 			#address-cells = <1>;
407 		cec: cec@40006c00 {
411 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
420 			clocks = <&rcc 1 CLK_UART7>;
424 		usart8: serial@40007c00 {
428 			clocks = <&rcc 1 CLK_UART8>;
433 			#address-cells = <1>;
455 			#address-cells = <1>;
480 			clocks = <&rcc 1 CLK_USART1>;
488 			clocks = <&rcc 1 CLK_USART6>;
492 		sdio2: mmc@40011c00 {
503 		sdio1: mmc@40012c00 {
515 			#address-cells = <1>;
525 			#address-cells = <1>;
540 		exti: interrupt-controller@40013c00 {
545 			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
549 			#address-cells = <1>;
599 			#address-cells = <1>;
609 			#address-cells = <1>;
623 			clocks = <&rcc 1 CLK_LCD>;
641 			#reset-cells = <1>;
647 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
708 	clocks = <&rcc 1 0>;