Lines Matching +full:0 +full:x400
53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
124 #size-cells = <0>;
126 reg = <0x40000800 0x400>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
146 #size-cells = <0>;
148 reg = <0x40000C00 0x400>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
168 #size-cells = <0>;
170 reg = <0x40001000 0x400>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
184 #size-cells = <0>;
186 reg = <0x40001400 0x400>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
200 #size-cells = <0>;
202 reg = <0x40001800 0x400>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
222 reg = <0x40001C00 0x400>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
236 reg = <0x40002000 0x400>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
250 reg = <0x40002800 0x400>;
256 st,syscfg = <&pwrcfg 0x00 0x100>;
262 reg = <0x40003400 0x200>;
266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
273 reg = <0x40003600 0x200>;
274 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
279 #size-cells = <0>;
281 reg = <0x40003800 0x400>;
283 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
289 #size-cells = <0>;
291 reg = <0x40003c00 0x400>;
293 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
299 reg = <0x40004400 0x400>;
307 reg = <0x40004800 0x400>;
315 reg = <0x40004c00 0x400>;
323 reg = <0x40005000 0x400>;
331 reg = <0x40005400 0x400>;
337 #size-cells = <0>;
343 reg = <0x40005800 0x400>;
349 #size-cells = <0>;
355 reg = <0x40005c00 0x400>;
361 #size-cells = <0>;
367 reg = <0x40006000 0x400>;
373 #size-cells = <0>;
379 reg = <0x40006400 0x200>;
383 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
391 reg = <0x40006600 0x200>;
392 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
397 reg = <0x40006800 0x200>;
401 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
409 reg = <0x40006C00 0x400>;
411 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
418 reg = <0x40007800 0x400>;
426 reg = <0x40007c00 0x400>;
434 #size-cells = <0>;
436 reg = <0x40010000 0x400>;
437 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
447 timer@0 {
449 reg = <0>;
456 #size-cells = <0>;
458 reg = <0x40010400 0x400>;
459 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
478 reg = <0x40011000 0x400>;
486 reg = <0x40011400 0x400>;
494 arm,primecell-periphid = <0x00880180>;
495 reg = <0x40011c00 0x400>;
496 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
505 arm,primecell-periphid = <0x00880180>;
506 reg = <0x40012c00 0x400>;
507 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
516 #size-cells = <0>;
518 reg = <0x40013000 0x400>;
520 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
526 #size-cells = <0>;
528 reg = <0x40013400 0x400>;
530 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
536 reg = <0x40013800 0x400>;
537 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
544 reg = <0x40013C00 0x400>;
550 #size-cells = <0>;
552 reg = <0x40014000 0x400>;
553 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
572 reg = <0x40014400 0x400>;
573 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
586 reg = <0x40014800 0x400>;
587 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
600 #size-cells = <0>;
602 reg = <0x40015000 0x400>;
604 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
610 #size-cells = <0>;
612 reg = <0x40015400 0x400>;
614 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
620 reg = <0x40016800 0x200>;
630 reg = <0x40007000 0x400>;
635 reg = <0x40023000 0x400>;
636 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
644 reg = <0x40023800 0x400>;
653 reg = <0x40026000 0x400>;
662 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
669 reg = <0x40026400 0x400>;
678 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
686 reg = <0x40040000 0x40000>;
688 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
698 reg = <0x50000000 0x40000>;
700 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
708 clocks = <&rcc 1 0>;