Lines Matching +full:cpg +full:- +full:mstp +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
26 clock-frequency = <1196000000>;
27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
28 power-domains = <&pd_a2sl>;
29 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <1196000000>;
36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
37 power-domains = <&pd_a2sl>;
38 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9-global-timer";
46 clocks = <&periph_clk>;
50 compatible = "arm,cortex-a9-twd-timer";
53 clocks = <&periph_clk>;
56 gic: interrupt-controller@f0001000 {
57 compatible = "arm,cortex-a9-gic";
58 #interrupt-cells = <3>;
59 interrupt-controller;
64 L2: cache-controller@f0100000 {
65 compatible = "arm,pl310-cache";
68 power-domains = <&pd_a3sm>;
69 arm,data-latency = <3 3 3>;
70 arm,tag-latency = <2 2 2>;
71 arm,shared-override;
72 cache-unified;
73 cache-level = <2>;
76 sbsc2: memory-controller@fb400000 {
77 compatible = "renesas,sbsc-sh73a0";
81 interrupt-names = "sec", "temp";
82 power-domains = <&pd_a4bc1>;
85 sbsc1: memory-controller@fe400000 {
86 compatible = "renesas,sbsc-sh73a0";
90 interrupt-names = "sec", "temp";
91 power-domains = <&pd_a4bc0>;
95 compatible = "arm,cortex-a9-pmu";
98 interrupt-affinity = <&cpu0>, <&cpu1>;
102 compatible = "renesas,sh73a0-cmt1";
105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
106 clock-names = "fck";
107 power-domains = <&pd_c5>;
111 irqpin0: interrupt-controller@e6900000 {
112 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
113 #interrupt-cells = <2>;
114 interrupt-controller;
128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
129 power-domains = <&pd_a4s>;
130 control-parent;
133 irqpin1: interrupt-controller@e6900004 {
134 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
135 #interrupt-cells = <2>;
136 interrupt-controller;
150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
151 power-domains = <&pd_a4s>;
152 control-parent;
155 irqpin2: interrupt-controller@e6900008 {
156 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
157 #interrupt-cells = <2>;
158 interrupt-controller;
172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
173 power-domains = <&pd_a4s>;
174 control-parent;
177 irqpin3: interrupt-controller@e690000c {
178 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
179 #interrupt-cells = <2>;
180 interrupt-controller;
194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
195 power-domains = <&pd_a4s>;
196 control-parent;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
209 power-domains = <&pd_a3sp>;
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
222 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
223 power-domains = <&pd_a3sp>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
236 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
237 power-domains = <&pd_a3sp>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
250 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
251 power-domains = <&pd_a3sp>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
264 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
265 power-domains = <&pd_c5>;
270 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
274 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
275 power-domains = <&pd_a3sp>;
276 reg-io-width = <4>;
281 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
284 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
285 power-domains = <&pd_a3sp>;
286 #address-cells = <1>;
287 #size-cells = <0>;
292 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
295 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
296 power-domains = <&pd_a3sp>;
297 #address-cells = <1>;
298 #size-cells = <0>;
303 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
306 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
307 power-domains = <&pd_a3sp>;
308 #address-cells = <1>;
309 #size-cells = <0>;
314 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
317 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
318 power-domains = <&pd_a3sp>;
319 #address-cells = <1>;
320 #size-cells = <0>;
325 compatible = "renesas,sdhi-sh73a0";
330 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
331 power-domains = <&pd_a3sp>;
332 cap-sd-highspeed;
338 compatible = "renesas,sdhi-sh73a0";
342 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
343 power-domains = <&pd_a3sp>;
344 disable-wp;
345 cap-sd-highspeed;
350 compatible = "renesas,sdhi-sh73a0";
354 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
355 power-domains = <&pd_a3sp>;
356 disable-wp;
357 cap-sd-highspeed;
362 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
365 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
366 clock-names = "fck";
367 power-domains = <&pd_a3sp>;
372 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
375 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
376 clock-names = "fck";
377 power-domains = <&pd_a3sp>;
382 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
385 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
386 clock-names = "fck";
387 power-domains = <&pd_a3sp>;
392 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
395 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
396 clock-names = "fck";
397 power-domains = <&pd_a3sp>;
402 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
405 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
406 clock-names = "fck";
407 power-domains = <&pd_a3sp>;
412 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
415 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
416 clock-names = "fck";
417 power-domains = <&pd_a3sp>;
422 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
425 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
426 clock-names = "fck";
427 power-domains = <&pd_a3sp>;
432 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
435 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
436 clock-names = "fck";
437 power-domains = <&pd_a3sp>;
442 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
445 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
446 clock-names = "fck";
447 power-domains = <&pd_a3sp>;
452 compatible = "renesas,pfc-sh73a0";
455 gpio-controller;
456 #gpio-cells = <2>;
457 gpio-ranges =
460 interrupts-extended =
469 power-domains = <&pd_c5>;
472 sysc: system-controller@e6180000 {
473 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
476 pm-domains {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 #power-domain-cells = <0>;
484 #power-domain-cells = <0>;
489 #power-domain-cells = <0>;
494 #power-domain-cells = <0>;
499 #power-domain-cells = <0>;
504 #power-domain-cells = <0>;
509 #power-domain-cells = <0>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 #power-domain-cells = <0>;
520 #power-domain-cells = <0>;
525 #power-domain-cells = <0>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 #power-domain-cells = <0>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <0>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 #power-domain-cells = <0>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 #power-domain-cells = <0>;
558 #power-domain-cells = <0>;
563 #power-domain-cells = <0>;
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #power-domain-cells = <0>;
574 #power-domain-cells = <0>;
583 #sound-dai-cells = <1>;
584 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
587 clocks = <&mstp3_clks SH73A0_CLK_FSI>;
588 power-domains = <&pd_a4mp>;
593 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
594 "simple-pm-bus";
595 #address-cells = <1>;
596 #size-cells = <1>;
600 clocks = <&zb_clk>;
601 power-domains = <&pd_a4s>;
604 clocks {
605 #address-cells = <1>;
606 #size-cells = <1>;
609 /* External root clocks */
611 compatible = "fixed-clock";
612 #clock-cells = <0>;
613 clock-frequency = <32768>;
616 compatible = "fixed-clock";
617 #clock-cells = <0>;
618 clock-frequency = <26000000>;
621 compatible = "fixed-clock";
622 #clock-cells = <0>;
624 clock-frequency = <0>;
627 compatible = "fixed-clock";
628 #clock-cells = <0>;
630 clock-frequency = <0>;
633 compatible = "fixed-clock";
634 #clock-cells = <0>;
636 clock-frequency = <0>;
639 compatible = "fixed-clock";
640 #clock-cells = <0>;
642 clock-frequency = <0>;
645 /* Special CPG clocks */
647 compatible = "renesas,sh73a0-cpg-clocks";
649 clocks = <&extal1_clk>, <&extal2_clk>;
650 #clock-cells = <1>;
651 clock-output-names = "main", "pll0", "pll1", "pll2",
657 /* Variable factor clocks (DIV6) */
659 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
661 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
665 #clock-cells = <0>;
668 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
670 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
674 #clock-cells = <0>;
677 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
679 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
683 #clock-cells = <0>;
686 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
688 clocks = <&pll1_div2_clk>, <0>,
690 #clock-cells = <0>;
691 clock-output-names = "zb";
694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
696 clocks = <&pll1_div2_clk>, <0>,
698 #clock-cells = <0>;
701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
703 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
705 #clock-cells = <0>;
708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
710 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
712 #clock-cells = <0>;
715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
717 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
719 #clock-cells = <0>;
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
724 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
726 #clock-cells = <0>;
729 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
731 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
733 #clock-cells = <0>;
736 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
738 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
740 #clock-cells = <0>;
743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
745 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
747 #clock-cells = <0>;
750 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
752 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
754 #clock-cells = <0>;
757 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
759 clocks = <&pll1_div2_clk>, <0>,
761 #clock-cells = <0>;
764 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
766 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
768 #clock-cells = <0>;
771 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
773 clocks = <&pll1_div2_clk>, <0>,
775 #clock-cells = <0>;
778 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
780 clocks = <&pll1_div2_clk>, <0>,
782 #clock-cells = <0>;
785 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
787 clocks = <&pll1_div2_clk>, <0>,
789 #clock-cells = <0>;
792 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
794 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
797 #clock-cells = <0>;
800 /* Fixed factor clocks */
802 compatible = "fixed-factor-clock";
803 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
804 #clock-cells = <0>;
805 clock-div = <2>;
806 clock-mult = <1>;
809 compatible = "fixed-factor-clock";
810 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
811 #clock-cells = <0>;
812 clock-div = <2>;
813 clock-mult = <1>;
816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
818 #clock-cells = <0>;
819 clock-div = <7>;
820 clock-mult = <1>;
823 compatible = "fixed-factor-clock";
824 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
825 #clock-cells = <0>;
826 clock-div = <13>;
827 clock-mult = <1>;
830 compatible = "fixed-factor-clock";
831 clocks = <&cpg_clocks SH73A0_CLK_Z>;
832 #clock-cells = <0>;
833 clock-div = <4>;
834 clock-mult = <1>;
837 /* Gate clocks */
839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
841 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
842 #clock-cells = <1>;
843 clock-indices = <
846 clock-output-names =
850 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
852 clocks = <&cpg_clocks SH73A0_CLK_B>,
860 #clock-cells = <1>;
861 clock-indices = <
868 clock-output-names =
873 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
875 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
880 #clock-cells = <1>;
881 clock-indices = <
890 clock-output-names =
897 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
899 clocks = <&sub_clk>, <&extalr_clk>,
908 #clock-cells = <1>;
909 clock-indices = <
919 clock-output-names =
925 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
927 clocks = <&cpg_clocks SH73A0_CLK_HP>,
929 #clock-cells = <1>;
930 clock-indices = <
934 clock-output-names =
938 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
940 clocks = <&cpg_clocks SH73A0_CLK_HP>;
941 #clock-cells = <1>;
942 clock-indices = <
945 clock-output-names =