Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
24 reg = <0x0>;
25 clock-frequency = <800000000>;
26 power-domains = <&pd_a3sm>;
27 next-level-cache = <&L2>;
31 gic: interrupt-controller@c2800000 {
33 #interrupt-cells = <3>;
34 interrupt-controller;
35 reg = <0xc2800000 0x1000>,
39 L2: cache-controller@f0100000 {
40 compatible = "arm,pl310-cache";
41 reg = <0xf0100000 0x1000>;
43 power-domains = <&pd_a3sm>;
44 arm,data-latency = <3 3 3>;
45 arm,tag-latency = <2 2 2>;
46 arm,shared-override;
47 cache-unified;
48 cache-level = <2>;
51 dbsc3: memory-controller@fe400000 {
52 compatible = "renesas,dbsc3-r8a7740";
53 reg = <0xfe400000 0x400>;
54 power-domains = <&pd_a4s>;
58 compatible = "arm,cortex-a9-pmu";
63 compatible = "arm,coresight-etm3x";
64 power-domains = <&pd_d4>;
68 reg = <0xfe910000 0x3000>;
69 compatible = "renesas,r8a7740-ceu";
72 power-domains = <&pd_a4r>;
77 reg = <0xfe914000 0x3000>;
78 compatible = "renesas,r8a7740-ceu";
81 power-domains = <&pd_a4r>;
86 compatible = "renesas,r8a7740-cmt1";
87 reg = <0xe6138000 0x170>;
90 clock-names = "fck";
91 power-domains = <&pd_c5>;
95 /* irqpin0: IRQ0 - IRQ7 */
96 irqpin0: interrupt-controller@e6900000 {
97 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 reg = <0xe6900000 4>,
114 power-domains = <&pd_a4s>;
117 /* irqpin1: IRQ8 - IRQ15 */
118 irqpin1: interrupt-controller@e6900004 {
119 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
120 #interrupt-cells = <2>;
121 interrupt-controller;
122 reg = <0xe6900004 4>,
136 power-domains = <&pd_a4s>;
139 /* irqpin2: IRQ16 - IRQ23 */
140 irqpin2: interrupt-controller@e6900008 {
141 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 reg = <0xe6900008 4>,
158 power-domains = <&pd_a4s>;
161 /* irqpin3: IRQ24 - IRQ31 */
162 irqpin3: interrupt-controller@e690000c {
163 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
164 #interrupt-cells = <2>;
165 interrupt-controller;
166 reg = <0xe690000c 4>,
180 power-domains = <&pd_a4s>;
184 compatible = "renesas,gether-r8a7740";
185 reg = <0xe9a00000 0x800>,
189 power-domains = <&pd_a4s>;
190 phy-mode = "mii";
191 #address-cells = <1>;
192 #size-cells = <0>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
200 reg = <0xfff20000 0x425>;
206 power-domains = <&pd_a4r>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
214 reg = <0xe6c20000 0x425>;
220 power-domains = <&pd_a3sp>;
225 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
226 reg = <0xe6c40000 0x100>;
229 clock-names = "fck";
230 power-domains = <&pd_a3sp>;
235 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
236 reg = <0xe6c50000 0x100>;
239 clock-names = "fck";
240 power-domains = <&pd_a3sp>;
245 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
246 reg = <0xe6c60000 0x100>;
249 clock-names = "fck";
250 power-domains = <&pd_a3sp>;
255 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
256 reg = <0xe6c70000 0x100>;
259 clock-names = "fck";
260 power-domains = <&pd_a3sp>;
265 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
266 reg = <0xe6c80000 0x100>;
269 clock-names = "fck";
270 power-domains = <&pd_a3sp>;
275 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
276 reg = <0xe6cb0000 0x100>;
279 clock-names = "fck";
280 power-domains = <&pd_a3sp>;
285 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
286 reg = <0xe6cc0000 0x100>;
289 clock-names = "fck";
290 power-domains = <&pd_a3sp>;
295 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
296 reg = <0xe6cd0000 0x100>;
299 clock-names = "fck";
300 power-domains = <&pd_a3sp>;
305 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
306 reg = <0xe6c30000 0x100>;
309 clock-names = "fck";
310 power-domains = <&pd_a3sp>;
315 compatible = "renesas,pfc-r8a7740";
316 reg = <0xe6050000 0x8000>,
318 gpio-controller;
319 #gpio-cells = <2>;
320 gpio-ranges = <&pfc 0 0 212>;
321 interrupts-extended =
330 power-domains = <&pd_c5>;
334 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
335 reg = <0xe6600000 0x148>;
337 power-domains = <&pd_a3sp>;
339 #pwm-cells = <3>;
343 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
344 reg = <0xe6bd0000 0x100>;
348 power-domains = <&pd_a3sp>;
353 compatible = "renesas,sdhi-r8a7740";
354 reg = <0xe6850000 0x100>;
359 power-domains = <&pd_a3sp>;
360 cap-sd-highspeed;
361 cap-sdio-irq;
366 compatible = "renesas,sdhi-r8a7740";
367 reg = <0xe6860000 0x100>;
372 power-domains = <&pd_a3sp>;
373 cap-sd-highspeed;
374 cap-sdio-irq;
379 compatible = "renesas,sdhi-r8a7740";
380 reg = <0xe6870000 0x100>;
385 power-domains = <&pd_a3sp>;
386 cap-sd-highspeed;
387 cap-sdio-irq;
392 #sound-dai-cells = <1>;
393 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
394 reg = <0xfe1f0000 0x400>;
397 power-domains = <&pd_a4mp>;
401 lcdc0: lcd-controller@fe940000 {
402 compatible = "renesas,r8a7740-lcdc";
403 reg = <0xfe940000 0x4000>;
408 clock-names = "fck", "media", "lclk", "video";
409 power-domains = <&pd_a4lc>;
413 #address-cells = <1>;
414 #size-cells = <0>;
417 reg = <0>;
425 lcdc1: lcd-controller@fe944000 {
426 compatible = "renesas,r8a7740-lcdc";
427 reg = <0xfe944000 0x4000>;
432 clock-names = "fck", "media", "lclk", "video";
433 power-domains = <&pd_a4lc>;
437 #address-cells = <1>;
438 #size-cells = <0>;
441 reg = <0>;
448 reg = <1>;
457 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
458 reg = <0xfff80000 0x2c>;
463 clock-names = "fck";
464 power-domains = <&pd_a4r>;
472 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
473 reg = <0xfff90000 0x2c>;
478 clock-names = "fck";
479 power-domains = <&pd_a4r>;
487 #address-cells = <1>;
488 #size-cells = <1>;
493 compatible = "fixed-clock";
494 #clock-cells = <0>;
495 clock-frequency = <32768>;
498 compatible = "fixed-clock";
499 #clock-cells = <0>;
500 clock-frequency = <0>;
503 compatible = "fixed-clock";
504 #clock-cells = <0>;
505 clock-frequency = <0>;
508 compatible = "fixed-clock";
509 #clock-cells = <0>;
510 clock-frequency = <27000000>;
513 compatible = "fixed-clock";
514 #clock-cells = <0>;
515 clock-frequency = <0>;
518 compatible = "fixed-clock";
519 #clock-cells = <0>;
520 clock-frequency = <0>;
523 compatible = "fixed-clock";
524 #clock-cells = <0>;
525 clock-frequency = <0>;
528 compatible = "fixed-clock";
529 #clock-cells = <0>;
530 clock-frequency = <0>;
533 compatible = "fixed-clock";
534 #clock-cells = <0>;
535 clock-frequency = <0>;
538 compatible = "fixed-clock";
539 #clock-cells = <0>;
540 clock-frequency = <0>;
545 compatible = "renesas,r8a7740-cpg-clocks";
546 reg = <0xe6150000 0x10000>;
548 #clock-cells = <1>;
549 clock-output-names = "system", "pllc0", "pllc1",
559 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
560 reg = <0xe6150008 4>;
565 #clock-cells = <0>;
568 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
569 reg = <0xe615000c 4>;
574 #clock-cells = <0>;
577 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
578 reg = <0xe6150010 4>;
580 #clock-cells = <0>;
583 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
584 reg = <0xe6150014 4>;
586 #clock-cells = <0>;
589 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
590 reg = <0xe6150018 4>;
592 #clock-cells = <0>;
595 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
596 reg = <0xe6150080 4>;
599 #clock-cells = <0>;
602 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
603 reg = <0xe6150084 4>;
606 #clock-cells = <0>;
609 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
610 reg = <0xe6150088 4>;
613 #clock-cells = <0>;
616 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
617 reg = <0xe615009c 4>;
619 #clock-cells = <0>;
624 compatible = "fixed-factor-clock";
626 #clock-cells = <0>;
627 clock-div = <2>;
628 clock-mult = <1>;
631 compatible = "fixed-factor-clock";
633 #clock-cells = <0>;
634 clock-div = <2>;
635 clock-mult = <1>;
640 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
641 reg = <0xe6150080 4>;
643 #clock-cells = <1>;
644 clock-indices = <
647 clock-output-names =
651 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
652 reg = <0xe6150134 4>, <0xe6150038 4>;
658 #clock-cells = <1>;
659 clock-indices = <
664 clock-output-names =
669 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
670 reg = <0xe6150138 4>, <0xe6150040 4>;
679 #clock-cells = <1>;
680 clock-indices = <
690 clock-output-names =
697 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
698 reg = <0xe615013c 4>, <0xe6150048 4>;
708 #clock-cells = <1>;
709 clock-indices = <
714 clock-output-names =
719 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
720 reg = <0xe6150140 4>, <0xe615004c 4>;
725 #clock-cells = <1>;
726 clock-indices = <
730 clock-output-names =
735 sysc: system-controller@e6180000 {
736 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
737 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
739 pm-domains {
741 #address-cells = <1>;
742 #size-cells = <0>;
743 #power-domain-cells = <0>;
746 reg = <1>;
747 #power-domain-cells = <0>;
751 reg = <2>;
752 #power-domain-cells = <0>;
756 reg = <3>;
757 #power-domain-cells = <0>;
761 reg = <5>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 #power-domain-cells = <0>;
767 reg = <6>;
768 #power-domain-cells = <0>;
773 reg = <10>;
774 #address-cells = <1>;
775 #size-cells = <0>;
776 #power-domain-cells = <0>;
779 reg = <11>;
780 #power-domain-cells = <0>;
784 reg = <12>;
785 #power-domain-cells = <0>;
789 reg = <13>;
790 #power-domain-cells = <0>;
795 reg = <20>;
796 #power-domain-cells = <0>;