dts/renesas/r8a7740.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 	interrupt-parent = <&gic>;
15 	#address-cells = <1>;
16 	#size-cells = <1>;
19 		#address-cells = <1>;
20 		#size-cells = <0>;
22 			compatible = "arm,cortex-a9";
25 			clock-frequency = <800000000>;
26 			power-domains = <&pd_a3sm>;
27 			next-level-cache = <&L2>;
31 	gic: interrupt-controller@c2800000 {
33 		#interrupt-cells = <3>;
34 		interrupt-controller;
39 	L2: cache-controller@f0100000 {
40 		compatible = "arm,pl310-cache";
43 		power-domains = <&pd_a3sm>;
44 		arm,data-latency = <3 3 3>;
45 		arm,tag-latency = <2 2 2>;
46 		arm,shared-override;
47 		cache-unified;
48 		cache-level = <2>;
51 	dbsc3: memory-controller@fe400000 {
52 		compatible = "renesas,dbsc3-r8a7740";
54 		power-domains = <&pd_a4s>;
58 		compatible = "arm,cortex-a9-pmu";
63 		compatible = "arm,coresight-etm3x";
64 		power-domains = <&pd_d4>;
69 		compatible = "renesas,r8a7740-ceu";
71 		clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
72 		power-domains = <&pd_a4r>;
78 		compatible = "renesas,r8a7740-ceu";
80 		clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
81 		power-domains = <&pd_a4r>;
86 		compatible = "renesas,r8a7740-cmt1";
89 		clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
90 		clock-names = "fck";
91 		power-domains = <&pd_c5>;
95 	/* irqpin0: IRQ0 - IRQ7 */
96 	irqpin0: interrupt-controller@e6900000 {
97 		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
98 		#interrupt-cells = <2>;
99 		interrupt-controller;
113 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
114 		power-domains = <&pd_a4s>;
117 	/* irqpin1: IRQ8 - IRQ15 */
118 	irqpin1: interrupt-controller@e6900004 {
119 		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
120 		#interrupt-cells = <2>;
121 		interrupt-controller;
135 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
136 		power-domains = <&pd_a4s>;
139 	/* irqpin2: IRQ16 - IRQ23 */
140 	irqpin2: interrupt-controller@e6900008 {
141 		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
142 		#interrupt-cells = <2>;
143 		interrupt-controller;
157 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
158 		power-domains = <&pd_a4s>;
161 	/* irqpin3: IRQ24 - IRQ31 */
162 	irqpin3: interrupt-controller@e690000c {
163 		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
164 		#interrupt-cells = <2>;
165 		interrupt-controller;
179 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
180 		power-domains = <&pd_a4s>;
184 		compatible = "renesas,gether-r8a7740";
188 		clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
189 		power-domains = <&pd_a4s>;
190 		phy-mode = "mii";
191 		#address-cells = <1>;
192 		#size-cells = <0>;
197 		#address-cells = <1>;
198 		#size-cells = <0>;
199 		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
205 		clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
206 		power-domains = <&pd_a4r>;
211 		#address-cells = <1>;
212 		#size-cells = <0>;
213 		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
219 		clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
220 		power-domains = <&pd_a3sp>;
225 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
228 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
229 		clock-names = "fck";
230 		power-domains = <&pd_a3sp>;
235 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
238 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
239 		clock-names = "fck";
240 		power-domains = <&pd_a3sp>;
245 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
248 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
249 		clock-names = "fck";
250 		power-domains = <&pd_a3sp>;
255 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
258 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
259 		clock-names = "fck";
260 		power-domains = <&pd_a3sp>;
265 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
268 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
269 		clock-names = "fck";
270 		power-domains = <&pd_a3sp>;
275 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
278 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
279 		clock-names = "fck";
280 		power-domains = <&pd_a3sp>;
285 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
288 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
289 		clock-names = "fck";
290 		power-domains = <&pd_a3sp>;
295 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
298 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
299 		clock-names = "fck";
300 		power-domains = <&pd_a3sp>;
305 		compatible = "renesas,scifb-r8a7740", "renesas,scifb";
308 		clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
309 		clock-names = "fck";
310 		power-domains = <&pd_a3sp>;
315 		compatible = "renesas,pfc-r8a7740";
318 		gpio-controller;
319 		#gpio-cells = <2>;
320 		gpio-ranges = <&pfc 0 0 212>;
321 		interrupts-extended =
330 		power-domains = <&pd_c5>;
334 		compatible = "renesas,tpu-r8a7740", "renesas,tpu";
336 		clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
337 		power-domains = <&pd_a3sp>;
339 		#pwm-cells = <3>;
343 		compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
347 		clocks = <&mstp3_clks R8A7740_CLK_MMC>;
348 		power-domains = <&pd_a3sp>;
353 		compatible = "renesas,sdhi-r8a7740";
358 		clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
359 		power-domains = <&pd_a3sp>;
360 		cap-sd-highspeed;
361 		cap-sdio-irq;
366 		compatible = "renesas,sdhi-r8a7740";
371 		clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
372 		power-domains = <&pd_a3sp>;
373 		cap-sd-highspeed;
374 		cap-sdio-irq;
379 		compatible = "renesas,sdhi-r8a7740";
384 		clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
385 		power-domains = <&pd_a3sp>;
386 		cap-sd-highspeed;
387 		cap-sdio-irq;
392 		#sound-dai-cells = <1>;
393 		compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
396 		clocks = <&mstp3_clks R8A7740_CLK_FSI>;
397 		power-domains = <&pd_a4mp>;
401 	lcdc0: lcd-controller@fe940000 {
402 		compatible = "renesas,r8a7740-lcdc";
405 		clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
408 		clock-names = "fck", "media", "lclk", "video";
409 		power-domains = <&pd_a4lc>;
413 			#address-cells = <1>;
414 			#size-cells = <0>;
425 	lcdc1: lcd-controller@fe944000 {
426 		compatible = "renesas,r8a7740-lcdc";
429 		clocks = <&mstp1_clks R8A7740_CLK_LCDC1>,
432 		clock-names = "fck", "media", "lclk", "video";
433 		power-domains = <&pd_a4lc>;
437 			#address-cells = <1>;
438 			#size-cells = <0>;
457 		compatible = "renesas,tmu-r8a7740", "renesas,tmu";
462 		clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
463 		clock-names = "fck";
464 		power-domains = <&pd_a4r>;
472 		compatible = "renesas,tmu-r8a7740", "renesas,tmu";
477 		clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
478 		clock-names = "fck";
479 		power-domains = <&pd_a4r>;
486 	clocks {
487 		#address-cells = <1>;
488 		#size-cells = <1>;
493 			compatible = "fixed-clock";
494 			#clock-cells = <0>;
495 			clock-frequency = <32768>;
498 			compatible = "fixed-clock";
499 			#clock-cells = <0>;
500 			clock-frequency = <0>;
503 			compatible = "fixed-clock";
504 			#clock-cells = <0>;
505 			clock-frequency = <0>;
508 			compatible = "fixed-clock";
509 			#clock-cells = <0>;
510 			clock-frequency = <27000000>;
513 			compatible = "fixed-clock";
514 			#clock-cells = <0>;
515 			clock-frequency = <0>;
518 			compatible = "fixed-clock";
519 			#clock-cells = <0>;
520 			clock-frequency = <0>;
523 			compatible = "fixed-clock";
524 			#clock-cells = <0>;
525 			clock-frequency = <0>;
528 			compatible = "fixed-clock";
529 			#clock-cells = <0>;
530 			clock-frequency = <0>;
533 			compatible = "fixed-clock";
534 			#clock-cells = <0>;
535 			clock-frequency = <0>;
538 			compatible = "fixed-clock";
539 			#clock-cells = <0>;
540 			clock-frequency = <0>;
543 		/* Special CPG clocks */
545 			compatible = "renesas,r8a7740-cpg-clocks";
547 			clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
548 			#clock-cells = <1>;
549 			clock-output-names = "system", "pllc0", "pllc1",
557 		/* Variable factor clocks (DIV6) */
559 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
561 			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
565 			#clock-cells = <0>;
568 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
570 			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
574 			#clock-cells = <0>;
577 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
579 			clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
580 			#clock-cells = <0>;
583 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
585 			clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
586 			#clock-cells = <0>;
589 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
591 			clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
592 			#clock-cells = <0>;
595 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
597 			clocks = <&pllc1_div2_clk>,
599 			#clock-cells = <0>;
602 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
604 			clocks = <&pllc1_div2_clk>,
606 			#clock-cells = <0>;
609 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
611 			clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
613 			#clock-cells = <0>;
616 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
618 			clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
619 			#clock-cells = <0>;
622 		/* Fixed factor clocks */
624 			compatible = "fixed-factor-clock";
625 			clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
626 			#clock-cells = <0>;
627 			clock-div = <2>;
628 			clock-mult = <1>;
631 			compatible = "fixed-factor-clock";
632 			clocks = <&extal1_clk>;
633 			#clock-cells = <0>;
634 			clock-div = <2>;
635 			clock-mult = <1>;
638 		/* Gate clocks */
640 			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
642 			clocks = <&sub_clk>, <&sub_clk>;
643 			#clock-cells = <1>;
644 			clock-indices = <
647 			clock-output-names =
651 			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
653 			clocks = <&cpg_clocks R8A7740_CLK_S>,
658 			#clock-cells = <1>;
659 			clock-indices = <
664 			clock-output-names =
669 			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
671 			clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
679 			#clock-cells = <1>;
680 			clock-indices = <
690 			clock-output-names =
697 			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
699 			clocks = <&cpg_clocks R8A7740_CLK_R>,
708 			#clock-cells = <1>;
709 			clock-indices = <
714 			clock-output-names =
719 			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
721 			clocks = <&cpg_clocks R8A7740_CLK_HP>,
725 			#clock-cells = <1>;
726 			clock-indices = <
730 			clock-output-names =
735 	sysc: system-controller@e6180000 {
736 		compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
739 		pm-domains {
741 				#address-cells = <1>;
742 				#size-cells = <0>;
743 				#power-domain-cells = <0>;
747 					#power-domain-cells = <0>;
752 					#power-domain-cells = <0>;
757 					#power-domain-cells = <0>;
762 					#address-cells = <1>;
763 					#size-cells = <0>;
764 					#power-domain-cells = <0>;
768 						#power-domain-cells = <0>;
774 					#address-cells = <1>;
775 					#size-cells = <0>;
776 					#power-domain-cells = <0>;
780 						#power-domain-cells = <0>;
785 						#power-domain-cells = <0>;
790 						#power-domain-cells = <0>;
796 					#power-domain-cells = <0>;