Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&intc>;
25 reg = <0x0 0x0>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <19200000>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32768>;
44 compatible = "qcom,scm-msm8226", "qcom,scm";
46 clock-names = "core", "bus", "iface";
51 compatible = "arm,cortex-a7-pmu";
57 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";
59 master-stats {
60 compatible = "qcom,rpm-master-stats";
61 qcom,rpm-msg-ram = <&apss_master_stats>,
65 qcom,master-names = "APSS",
71 smd-edge {
74 qcom,smd-edge = <15>;
76 rpm_requests: rpm-requests {
77 compatible = "qcom,rpm-msm8226";
78 qcom,smd-channels = "rpm_requests";
80 rpmcc: clock-controller {
81 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
82 #clock-cells = <1>;
84 clock-names = "xo";
87 rpmpd: power-controller {
88 compatible = "qcom,msm8226-rpmpd";
89 #power-domain-cells = <1>;
90 operating-points-v2 = <&rpmpd_opp_table>;
92 rpmpd_opp_table: opp-table {
93 compatible = "operating-points-v2";
96 opp-level = <1>;
99 opp-level = <2>;
102 opp-level = <3>;
105 opp-level = <4>;
108 opp-level = <5>;
111 opp-level = <6>;
119 reserved-memory {
120 #address-cells = <1>;
121 #size-cells = <1>;
125 reg = <0x3000000 0x100000>;
126 no-map;
130 reg = <0x0dc00000 0x1900000>;
131 no-map;
138 memory-region = <&smem_region>;
139 qcom,rpm-msg-ram = <&rpm_msg_ram>;
144 smp2p-adsp {
148 interrupt-parent = <&intc>;
153 qcom,local-pid = <0>;
154 qcom,remote-pid = <2>;
156 adsp_smp2p_out: master-kernel {
157 qcom,entry-name = "master-kernel";
158 #qcom,smem-state-cells = <1>;
161 adsp_smp2p_in: slave-kernel {
162 qcom,entry-name = "slave-kernel";
164 interrupt-controller;
165 #interrupt-cells = <2>;
170 compatible = "simple-bus";
171 #address-cells = <1>;
172 #size-cells = <1>;
175 intc: interrupt-controller@f9000000 {
176 compatible = "qcom,msm-qgic2";
177 reg = <0xf9000000 0x1000>,
179 interrupt-controller;
180 #interrupt-cells = <3>;
185 reg = <0xf9011000 0x1000>;
189 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
190 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
191 reg-names = "hc", "core";
194 interrupt-names = "hc_irq", "pwr_irq";
198 clock-names = "iface", "core", "xo";
199 pinctrl-names = "default";
200 pinctrl-0 = <&sdhc1_default_state>;
205 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
206 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
207 reg-names = "hc", "core";
210 interrupt-names = "hc_irq", "pwr_irq";
214 clock-names = "iface", "core", "xo";
215 pinctrl-names = "default";
216 pinctrl-0 = <&sdhc2_default_state>;
221 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
222 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
223 reg-names = "hc", "core";
226 interrupt-names = "hc_irq", "pwr_irq";
230 clock-names = "iface", "core", "xo";
231 pinctrl-names = "default";
232 pinctrl-0 = <&sdhc3_default_state>;
237 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
238 reg = <0xf991d000 0x1000>;
241 clock-names = "core", "iface";
246 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
247 reg = <0xf991e000 0x1000>;
251 clock-names = "core",
257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
258 reg = <0xf991f000 0x1000>;
261 clock-names = "core", "iface";
266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
267 reg = <0xf9920000 0x1000>;
270 clock-names = "core", "iface";
276 compatible = "qcom,i2c-qup-v2.1.1";
277 reg = <0xf9923000 0x1000>;
280 clock-names = "core", "iface";
281 pinctrl-names = "default";
282 pinctrl-0 = <&blsp1_i2c1_pins>;
283 #address-cells = <1>;
284 #size-cells = <0>;
289 compatible = "qcom,i2c-qup-v2.1.1";
290 reg = <0xf9924000 0x1000>;
293 clock-names = "core", "iface";
294 pinctrl-names = "default";
295 pinctrl-0 = <&blsp1_i2c2_pins>;
296 #address-cells = <1>;
297 #size-cells = <0>;
302 compatible = "qcom,i2c-qup-v2.1.1";
303 reg = <0xf9925000 0x1000>;
306 clock-names = "core", "iface";
307 pinctrl-names = "default";
308 pinctrl-0 = <&blsp1_i2c3_pins>;
309 #address-cells = <1>;
310 #size-cells = <0>;
315 compatible = "qcom,i2c-qup-v2.1.1";
316 reg = <0xf9926000 0x1000>;
319 clock-names = "core", "iface";
320 pinctrl-names = "default";
321 pinctrl-0 = <&blsp1_i2c4_pins>;
322 #address-cells = <1>;
323 #size-cells = <0>;
328 compatible = "qcom,i2c-qup-v2.1.1";
329 reg = <0xf9927000 0x1000>;
332 clock-names = "core", "iface";
333 pinctrl-names = "default";
334 pinctrl-0 = <&blsp1_i2c5_pins>;
335 #address-cells = <1>;
336 #size-cells = <0>;
340 compatible = "qcom,i2c-qup-v2.1.1";
341 reg = <0xf9928000 0x1000>;
345 clock-names = "core",
347 pinctrl-0 = <&blsp1_i2c6_pins>;
348 pinctrl-names = "default";
349 #address-cells = <1>;
350 #size-cells = <0>;
355 compatible = "qcom,msm8226-cci";
356 #address-cells = <1>;
357 #size-cells = <0>;
358 reg = <0xfda0c000 0x1000>;
363 clock-names = "camss_top_ahb",
367 pinctrl-names = "default", "sleep";
368 pinctrl-0 = <&cci_default>;
369 pinctrl-1 = <&cci_sleep>;
373 cci_i2c0: i2c-bus@0 {
374 reg = <0>;
375 clock-frequency = <400000>;
376 #address-cells = <1>;
377 #size-cells = <0>;
382 compatible = "qcom,ci-hdrc";
383 reg = <0xf9a55000 0x200>,
388 clock-names = "iface", "core";
389 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
390 assigned-clock-rates = <75000000>;
392 reset-names = "core";
395 hnp-disable;
396 srp-disable;
397 adp-disable;
398 ahb-burst-config = <0>;
399 phy-names = "usb-phy";
402 #reset-cells = <1>;
406 compatible = "qcom,usb-hs-phy-msm8226",
407 "qcom,usb-hs-phy";
408 #phy-cells = <0>;
411 clock-names = "ref", "sleep";
413 reset-names = "phy", "por";
414 qcom,init-seq = /bits/ 8 <0x0 0x44
420 gcc: clock-controller@fc400000 {
421 compatible = "qcom,gcc-msm8226";
422 reg = <0xfc400000 0x4000>;
423 #clock-cells = <1>;
424 #reset-cells = <1>;
425 #power-domain-cells = <1>;
429 clock-names = "xo",
433 mmcc: clock-controller@fd8c0000 {
434 compatible = "qcom,mmcc-msm8226";
435 reg = <0xfd8c0000 0x6000>;
436 #clock-cells = <1>;
437 #reset-cells = <1>;
438 #power-domain-cells = <1>;
447 clock-names = "xo",
457 compatible = "qcom,msm8226-pinctrl";
458 reg = <0xfd510000 0x4000>;
459 gpio-controller;
460 #gpio-cells = <2>;
461 gpio-ranges = <&tlmm 0 0 117>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
466 blsp1_i2c1_pins: blsp1-i2c1-state {
469 drive-strength = <2>;
470 bias-disable;
473 blsp1_i2c2_pins: blsp1-i2c2-state {
476 drive-strength = <2>;
477 bias-disable;
480 blsp1_i2c3_pins: blsp1-i2c3-state {
483 drive-strength = <2>;
484 bias-disable;
487 blsp1_i2c4_pins: blsp1-i2c4-state {
490 drive-strength = <2>;
491 bias-disable;
494 blsp1_i2c5_pins: blsp1-i2c5-state {
497 drive-strength = <2>;
498 bias-disable;
501 blsp1_i2c6_pins: blsp1-i2c6-state {
504 drive-strength = <2>;
505 bias-disable;
508 cci_default: cci-default-state {
512 drive-strength = <2>;
513 bias-disable;
516 cci_sleep: cci-sleep-state {
520 drive-strength = <2>;
521 bias-disable;
524 sdhc1_default_state: sdhc1-default-state {
525 clk-pins {
527 drive-strength = <10>;
528 bias-disable;
531 cmd-data-pins {
533 drive-strength = <10>;
534 bias-pull-up;
538 sdhc2_default_state: sdhc2-default-state {
539 clk-pins {
541 drive-strength = <10>;
542 bias-disable;
545 cmd-data-pins {
547 drive-strength = <10>;
548 bias-pull-up;
552 sdhc3_default_state: sdhc3-default-state {
553 clk-pins {
556 drive-strength = <8>;
557 bias-disable;
560 cmd-pins {
563 drive-strength = <8>;
564 bias-pull-up;
567 data-pins {
570 drive-strength = <8>;
571 bias-pull-up;
576 tsens: thermal-sensor@fc4a9000 {
577 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
578 reg = <0xfc4a9000 0x1000>, /* TM */
580 nvmem-cells = <&tsens_mode>,
589 nvmem-cell-names = "mode",
600 interrupt-names = "uplow";
601 #thermal-sensor-cells = <1>;
606 reg = <0xfc4ab000 0x4>;
610 compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
611 reg = <0xfc4bc000 0x1000>;
612 #address-cells = <1>;
613 #size-cells = <1>;
616 reg = <0x1c1 0x2>;
620 tsens_s0_p1: s0-p1@1c2 {
621 reg = <0x1c2 0x2>;
625 tsens_s1_p1: s1-p1@1c4 {
626 reg = <0x1c4 0x1>;
630 tsens_s2_p1: s2-p1@1c4 {
631 reg = <0x1c4 0x2>;
635 tsens_s3_p1: s3-p1@1c5 {
636 reg = <0x1c5 0x2>;
640 tsens_s4_p1: s4-p1@1c6 {
641 reg = <0x1c6 0x1>;
645 tsens_s5_p1: s5-p1@1c7 {
646 reg = <0x1c7 0x1>;
650 tsens_s6_p1: s6-p1@1ca {
651 reg = <0x1ca 0x2>;
656 reg = <0x1cc 0x1>;
660 tsens_s0_p2: s0-p2@1cd {
661 reg = <0x1cd 0x1>;
665 tsens_s1_p2: s1-p2@1cd {
666 reg = <0x1cd 0x2>;
670 tsens_s2_p2: s2-p2@1ce {
671 reg = <0x1ce 0x2>;
675 tsens_s3_p2: s3-p2@1cf {
676 reg = <0x1cf 0x1>;
680 tsens_s4_p2: s4-p2@446 {
681 reg = <0x446 0x2>;
685 tsens_s5_p2: s5-p2@447 {
686 reg = <0x447 0x1>;
690 tsens_s6_p2: s6-p2@44e {
691 reg = <0x44e 0x1>;
696 reg = <0x44f 0x1>;
702 compatible = "qcom,spmi-pmic-arb";
703 reg-names = "core", "intr", "cnfg";
704 reg = <0xfc4cf000 0x1000>,
707 interrupt-names = "periph_irq";
711 #address-cells = <2>;
712 #size-cells = <0>;
713 interrupt-controller;
714 #interrupt-cells = <4>;
719 reg = <0xf9bff000 0x200>;
721 clock-names = "core";
725 compatible = "arm,armv7-timer-mem";
726 reg = <0xf9020000 0x1000>;
727 #address-cells = <1>;
728 #size-cells = <1>;
732 frame-number = <0>;
735 reg = <0xf9021000 0x1000>,
740 frame-number = <1>;
742 reg = <0xf9023000 0x1000>;
747 frame-number = <2>;
749 reg = <0xf9024000 0x1000>;
754 frame-number = <3>;
756 reg = <0xf9025000 0x1000>;
761 frame-number = <4>;
763 reg = <0xf9026000 0x1000>;
768 frame-number = <5>;
770 reg = <0xf9027000 0x1000>;
775 frame-number = <6>;
777 reg = <0xf9028000 0x1000>;
783 compatible = "qcom,msm8226-rpm-stats";
784 reg = <0xfc190000 0x10000>;
788 compatible = "qcom,rpm-msg-ram";
789 reg = <0xfc428000 0x4000>;
791 #address-cells = <1>;
792 #size-cells = <1>;
796 reg = <0x150 0x14>;
800 reg = <0xb50 0x14>;
804 reg = <0x1550 0x14>;
808 reg = <0x1f50 0x14>;
813 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
814 reg = <0xfd484000 0x1000>;
815 #hwlock-cells = <1>;
819 compatible = "qcom,msm8226-adsp-pil";
820 reg = <0xfe200000 0x100>;
822 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
827 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
829 power-domains = <&rpmpd MSM8226_VDDCX>;
830 power-domain-names = "cx";
833 clock-names = "xo";
835 memory-region = <&adsp_region>;
837 qcom,smem-states = <&adsp_smp2p_out 0>;
838 qcom,smem-state-names = "stop";
842 smd-edge {
846 qcom,smd-edge = <1>;
853 compatible = "qcom,msm8226-ocmem";
854 reg = <0xfdd00000 0x2000>,
856 reg-names = "ctrl", "mem";
859 clock-names = "core";
861 #address-cells = <1>;
862 #size-cells = <1>;
864 gmu_sram: gmu-sram@0 {
865 reg = <0x0 0x20000>;
870 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
871 reg = <0xfe805000 0x1000>;
873 reboot-mode {
874 compatible = "syscon-reboot-mode";
877 mode-bootloader = <0x77665500>;
878 mode-normal = <0x77665501>;
879 mode-recovery = <0x77665502>;
883 mdss: display-subsystem@fd900000 {
885 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
886 reg-names = "mdss_phys", "vbif_phys";
888 power-domains = <&mmcc MDSS_GDSC>;
893 clock-names = "iface",
899 interrupt-controller;
900 #interrupt-cells = <1>;
902 #address-cells = <1>;
903 #size-cells = <1>;
908 mdss_mdp: display-controller@fd900000 {
909 compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
910 reg = <0xfd900100 0x22000>;
911 reg-names = "mdp_phys";
913 interrupt-parent = <&mdss>;
920 clock-names = "iface",
926 #address-cells = <1>;
927 #size-cells = <0>;
930 reg = <0>;
932 remote-endpoint = <&mdss_dsi0_in>;
939 compatible = "qcom,msm8226-dsi-ctrl",
940 "qcom,mdss-dsi-ctrl";
941 reg = <0xfd922800 0x1f8>;
942 reg-names = "dsi_ctrl";
944 interrupt-parent = <&mdss>;
947 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
949 assigned-clock-parents = <&mdss_dsi0_phy 0>,
959 clock-names = "mdp_core",
969 #address-cells = <1>;
970 #size-cells = <0>;
973 #address-cells = <1>;
974 #size-cells = <0>;
977 reg = <0>;
979 remote-endpoint = <&mdss_mdp_intf1_out>;
984 reg = <1>;
992 compatible = "qcom,dsi-phy-28nm-8226";
993 reg = <0xfd922a00 0xd4>,
996 reg-names = "dsi_pll",
1000 #clock-cells = <1>;
1001 #phy-cells = <0>;
1005 clock-names = "iface",
1011 compatible = "qcom,adreno-305.18", "qcom,adreno";
1012 reg = <0xfdb00000 0x10000>;
1013 reg-names = "kgsl_3d0_reg_memory";
1016 interrupt-names = "kgsl_3d0_irq";
1021 clock-names = "core", "iface", "mem_iface";
1024 power-domains = <&mmcc OXILICX_GDSC>;
1025 operating-points-v2 = <&gpu_opp_table>;
1029 gpu_opp_table: opp-table {
1030 compatible = "operating-points-v2";
1032 opp-450000000 {
1033 opp-hz = /bits/ 64 <450000000>;
1036 opp-320000000 {
1037 opp-hz = /bits/ 64 <320000000>;
1040 opp-200000000 {
1041 opp-hz = /bits/ 64 <200000000>;
1044 opp-19000000 {
1045 opp-hz = /bits/ 64 <19000000>;
1051 thermal-zones {
1052 cpu0-thermal {
1053 polling-delay-passive = <250>;
1054 polling-delay = <1000>;
1056 thermal-sensors = <&tsens 5>;
1073 cpu1-thermal {
1074 polling-delay-passive = <250>;
1075 polling-delay = <1000>;
1077 thermal-sensors = <&tsens 2>;
1096 compatible = "arm,armv7-timer";