Lines Matching +full:1 +full:a01000
13 #address-cells = <1>;
14 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <1>;
36 #address-cells = <1>;
50 CPU1: cpu@1 {
54 reg = <1>;
193 interrupts = <1 10 0x304>;
219 #hwlock-cells = <1>;
232 #address-cells = <1>;
235 qcom,ipc-1 = <&l2cc 8 4>;
242 #qcom,smem-state-cells = <1>;
245 modem_smsm: modem@1 {
246 reg = <1>;
288 #address-cells = <1>;
289 #size-cells = <1>;
324 interrupts = <1 1 0x301>,
325 <1 2 0x301>,
326 <1 3 0x301>;
369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
375 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
381 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
387 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
400 cell-index = <1>;
404 #address-cells = <1>;
405 #size-cells = <1>;
423 pinctrl-1 = <&i2c1_pins_sleep>;
429 #address-cells = <1>;
443 #address-cells = <1>;
444 #size-cells = <1>;
453 pinctrl-1 = <&i2c2_pins_sleep>;
458 #address-cells = <1>;
471 #address-cells = <1>;
472 #size-cells = <1>;
477 pinctrl-1 = <&i2c3_pins_sleep>;
484 #address-cells = <1>;
497 #address-cells = <1>;
498 #size-cells = <1>;
516 pinctrl-1 = <&i2c4_pins_sleep>;
527 gsbi5: gsbi@1a200000 {
534 #address-cells = <1>;
535 #size-cells = <1>;
538 gsbi5_serial: serial@1a240000 {
548 gsbi5_spi: spi@1a280000 {
553 pinctrl-1 = <&spi5_sleep>;
558 #address-cells = <1>;
570 #address-cells = <1>;
571 #size-cells = <1>;
587 pinctrl-1 = <&i2c6_pins_sleep>;
605 #address-cells = <1>;
606 #size-cells = <1>;
623 pinctrl-1 = <&i2c7_pins_sleep>;
634 rng@1a500000 {
656 #address-cells = <1>;
657 #size-cells = <1>;
670 #clock-cells = <1>;
671 #power-domain-cells = <1>;
672 #reset-cells = <1>;
687 #thermal-sensor-cells = <1>;
694 #clock-cells = <1>;
695 #reset-cells = <1>;
715 #clock-cells = <1>;
716 #power-domain-cells = <1>;
717 #reset-cells = <1>;
721 <&dsi0_phy 1>,
723 <&dsi1_phy 1>,
756 #clock-cells = <1>;
778 #reset-cells = <1>;
809 #reset-cells = <1>;
840 #reset-cells = <1>;
855 sata_phy0: phy@1b400000 {
903 no-1-8-v;
904 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
914 #dma-cells = <1>;
930 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
942 #dma-cells = <1>;
961 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
971 #dma-cells = <1>;
975 tcsr: syscon@1a400000 {
998 &gfx3d 1
1030 &gfx3d1 1
1085 #address-cells = <1>;
1108 <&dsi0_phy 1>,
1109 <&dsi0_phy 1>;
1115 #address-cells = <1>;
1124 port@1 {
1125 reg = <1>;
1135 #clock-cells = <1>;
1175 <&dsi1_phy 1>,
1176 <&dsi1_phy 1>;
1181 #address-cells = <1>;
1187 #address-cells = <1>;
1196 port@1 {
1197 reg = <1>;
1217 #clock-cells = <1>;
1225 #iommu-cells = <1>;
1241 #iommu-cells = <1>;
1257 #iommu-cells = <1>;
1273 #iommu-cells = <1>;
1287 pcie: pcie@1b500000 {
1297 num-lanes = <1>;
1304 #interrupt-cells = <1>;
1306 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1342 #address-cells = <1>;
1351 port@1 {
1352 reg = <1>;
1397 #address-cells = <1>;
1406 port@1 {
1407 reg = <1>;
1479 etb@1a01000 {
1495 tpiu@1a03000 {
1518 #address-cells = <1>;
1527 port@1 {
1528 reg = <1>;
1544 funnel@1a04000 {
1552 #address-cells = <1>;
1568 port@1 {
1569 reg = <1>;
1597 etm@1a1c000 {
1615 etm@1a1d000 {
1633 etm@1a1e000 {
1651 etm@1a1f000 {