Lines Matching +full:imx21 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
19 * pre-existing /chosen node to be available to insert the
55 #address-cells = <1>;
56 #size-cells = <0>;
58 idle-states {
59 entry-method = "psci";
61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x0010000>;
64 local-timer-stop;
65 entry-latency-us = <100>;
66 exit-latency-us = <50>;
67 min-residency-us = <1000>;
72 compatible = "arm,cortex-a7";
75 clock-frequency = <792000000>;
76 clock-latency = <61036>; /* two CLK32 periods */
78 cpu-idle-states = <&cpu_sleep_wait>;
79 operating-points-v2 = <&cpu0_opp_table>;
80 #cooling-cells = <2>;
81 nvmem-cells = <&fuse_grade>;
82 nvmem-cell-names = "speed_grade";
86 cpu0_opp_table: opp-table {
87 compatible = "operating-points-v2";
88 opp-shared;
90 opp-792000000 {
91 opp-hz = /bits/ 64 <792000000>;
92 opp-microvolt = <1000000>;
93 clock-latency-ns = <150000>;
94 opp-supported-hw = <0xf>, <0xf>;
98 ckil: clock-cki {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
113 compatible = "usb-nop-xceiv";
115 clock-names = "main_clk";
116 #phy-cells = <0>;
120 compatible = "usb-nop-xceiv";
122 clock-names = "main_clk";
123 power-domains = <&pgc_hsic_phy>;
124 #phy-cells = <0>;
128 compatible = "arm,cortex-a7-pmu";
129 interrupt-parent = <&gpc>;
131 interrupt-affinity = <&cpu0>;
136 * non-configurable replicators don't show up on the
139 compatible = "arm,coresight-static-replicator";
141 out-ports {
142 #address-cells = <1>;
143 #size-cells = <0>;
148 remote-endpoint = <&tpiu_in_port>;
155 remote-endpoint = <&etr_in_port>;
160 in-ports {
163 remote-endpoint = <&etf_out_port>;
170 compatible = "arm,armv7-timer";
171 arm,cpu-registers-not-fw-configured;
172 interrupt-parent = <&intc>;
180 #address-cells = <1>;
181 #size-cells = <1>;
182 compatible = "simple-bus";
183 interrupt-parent = <&gpc>;
187 compatible = "mmio-sram";
190 #address-cells = <1>;
191 #size-cells = <1>;
196 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
199 clock-names = "apb_pclk";
201 ca_funnel_in_ports: in-ports {
202 #address-cells = <1>;
203 #size-cells = <0>;
208 remote-endpoint = <&etm0_out_port>;
215 out-ports {
218 remote-endpoint = <&hugo_funnel_in_port0>;
226 compatible = "arm,coresight-etm3x", "arm,primecell";
230 clock-names = "apb_pclk";
232 out-ports {
235 remote-endpoint = <&ca_funnel_in_port0>;
242 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
245 clock-names = "apb_pclk";
247 in-ports {
248 #address-cells = <1>;
249 #size-cells = <0>;
254 remote-endpoint = <&ca_funnel_out_port0>;
267 out-ports {
270 remote-endpoint = <&etf_in_port>;
277 compatible = "arm,coresight-tmc", "arm,primecell";
280 clock-names = "apb_pclk";
282 in-ports {
285 remote-endpoint = <&hugo_funnel_out_port0>;
290 out-ports {
293 remote-endpoint = <&replicator_in_port0>;
300 compatible = "arm,coresight-tmc", "arm,primecell";
303 clock-names = "apb_pclk";
305 in-ports {
308 remote-endpoint = <&replicator_out_port1>;
315 compatible = "arm,coresight-tpiu", "arm,primecell";
318 clock-names = "apb_pclk";
320 in-ports {
323 remote-endpoint = <&replicator_out_port0>;
329 intc: interrupt-controller@31001000 {
330 compatible = "arm,cortex-a7-gic";
332 #interrupt-cells = <3>;
333 interrupt-controller;
334 interrupt-parent = <&intc>;
342 compatible = "fsl,aips-bus", "simple-bus";
343 #address-cells = <1>;
344 #size-cells = <1>;
349 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
361 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
365 gpio-controller;
366 #gpio-cells = <2>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 gpio-ranges = <&iomuxc 0 13 32>;
373 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
377 gpio-controller;
378 #gpio-cells = <2>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
381 gpio-ranges = <&iomuxc 0 45 29>;
385 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
389 gpio-controller;
390 #gpio-cells = <2>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
393 gpio-ranges = <&iomuxc 0 74 24>;
397 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 gpio-ranges = <&iomuxc 0 98 18>;
409 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 gpio-ranges = <&iomuxc 0 116 23>;
421 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
425 gpio-controller;
426 #gpio-cells = <2>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 gpio-ranges = <&iomuxc 0 139 16>;
433 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
440 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
448 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
456 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
464 compatible = "fsl,imx7d-iomuxc-lpsr";
466 fsl,input-sel = <&iomuxc>;
470 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
475 clock-names = "ipg", "per";
479 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
484 clock-names = "ipg", "per";
489 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
494 clock-names = "ipg", "per";
499 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
504 clock-names = "ipg", "per";
509 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
517 compatible = "fsl,imx7d-iomuxc";
521 gpr: iomuxc-gpr@30340000 {
522 compatible = "fsl,imx7d-iomuxc-gpr",
523 "fsl,imx6q-iomuxc-gpr", "syscon",
524 "simple-mfd";
527 mux: mux-controller {
528 compatible = "mmio-mux";
529 #mux-control-cells = <1>;
530 mux-reg-masks = <0x14 0x00000010>;
533 video_mux: csi-mux {
534 compatible = "video-mux";
535 mux-controls = <&mux 0>;
536 #address-cells = <1>;
537 #size-cells = <0>;
548 remote-endpoint = <&mipi_vc0_to_csi_mux>;
556 remote-endpoint = <&csi_from_csi_mux>;
563 #address-cells = <1>;
564 #size-cells = <1>;
565 compatible = "fsl,imx7d-ocotp", "syscon";
573 fuse_grade: fuse-grade@10 {
579 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
580 "syscon", "simple-mfd";
585 reg_1p0d: regulator-vdd1p0d {
586 compatible = "fsl,anatop-regulator";
587 regulator-name = "vdd1p0d";
588 regulator-min-microvolt = <800000>;
589 regulator-max-microvolt = <1200000>;
590 anatop-reg-offset = <0x210>;
591 anatop-vol-bit-shift = <8>;
592 anatop-vol-bit-width = <5>;
593 anatop-min-bit-val = <8>;
594 anatop-min-voltage = <800000>;
595 anatop-max-voltage = <1200000>;
596 anatop-enable-bit = <0>;
599 reg_1p2: regulator-vdd1p2 {
600 compatible = "fsl,anatop-regulator";
601 regulator-name = "vdd1p2";
602 regulator-min-microvolt = <1100000>;
603 regulator-max-microvolt = <1300000>;
604 anatop-reg-offset = <0x220>;
605 anatop-vol-bit-shift = <8>;
606 anatop-vol-bit-width = <5>;
607 anatop-min-bit-val = <0x14>;
608 anatop-min-voltage = <1100000>;
609 anatop-max-voltage = <1300000>;
610 anatop-enable-bit = <0>;
614 compatible = "fsl,imx7d-tempmon";
615 interrupt-parent = <&gpc>;
618 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
619 nvmem-cell-names = "calib", "temp_grade";
621 #thermal-sensor-cells = <0>;
626 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
629 snvs_rtc: snvs-rtc-lp {
630 compatible = "fsl,sec-v4.0-mon-rtc-lp";
636 clock-names = "snvs-rtc";
639 snvs_pwrkey: snvs-powerkey {
640 compatible = "fsl,sec-v4.0-pwrkey";
644 clock-names = "snvs-pwrkey";
646 wakeup-source;
651 clks: clock-controller@30380000 {
652 compatible = "fsl,imx7d-ccm";
656 #clock-cells = <1>;
658 clock-names = "ckil", "osc";
661 src: reset-controller@30390000 {
662 compatible = "fsl,imx7d-src", "syscon";
665 #reset-cells = <1>;
669 compatible = "fsl,imx7d-gpc";
671 interrupt-controller;
673 #interrupt-cells = <3>;
674 interrupt-parent = <&intc>;
677 #address-cells = <1>;
678 #size-cells = <0>;
680 pgc_mipi_phy: power-domain@0 {
681 #power-domain-cells = <0>;
683 power-supply = <®_1p0d>;
686 pgc_pcie_phy: power-domain@1 {
687 #power-domain-cells = <0>;
689 power-supply = <®_1p0d>;
692 pgc_hsic_phy: power-domain@2 {
693 #power-domain-cells = <0>;
695 power-supply = <®_1p2>;
702 compatible = "fsl,aips-bus", "simple-bus";
703 #address-cells = <1>;
704 #size-cells = <1>;
709 compatible = "fsl,imx7d-adc";
713 clock-names = "adc";
714 #io-channel-cells = <1>;
719 compatible = "fsl,imx7d-adc";
723 clock-names = "adc";
724 #io-channel-cells = <1>;
729 #address-cells = <1>;
730 #size-cells = <0>;
731 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
736 clock-names = "ipg", "per";
737 dma-names = "rx", "tx";
743 compatible = "fsl,vf610-ftm-pwm";
745 #pwm-cells = <3>;
747 clock-names = "ftm_sys", "ftm_ext",
757 compatible = "fsl,vf610-ftm-pwm";
759 #pwm-cells = <3>;
761 clock-names = "ftm_sys", "ftm_ext",
771 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
776 clock-names = "ipg", "per";
777 #pwm-cells = <3>;
782 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
787 clock-names = "ipg", "per";
788 #pwm-cells = <3>;
793 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
798 clock-names = "ipg", "per";
799 #pwm-cells = <3>;
804 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
809 clock-names = "ipg", "per";
810 #pwm-cells = <3>;
815 compatible = "fsl,imx7-csi";
819 clock-names = "mclk";
824 remote-endpoint = <&csi_mux_to_csi>;
830 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
835 clock-names = "pix", "axi";
839 mipi_csi: mipi-csi@30750000 {
840 compatible = "fsl,imx7-mipi-csi2";
846 clock-names = "pclk", "wrap", "phy";
847 power-domains = <&pgc_mipi_phy>;
848 phy-supply = <®_1p0d>;
853 #address-cells = <1>;
854 #size-cells = <0>;
864 remote-endpoint = <&csi_mux_from_mipi_vc0>;
871 compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim";
872 #address-cells = <1>;
873 #size-cells = <0>;
877 clock-names = "bus_clk", "sclk_mipi";
878 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
880 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
881 assigned-clock-rates = <0>, <333000000>;
882 power-domains = <&pgc_mipi_phy>;
884 samsung,burst-clock-frequency = <891000000>;
885 samsung,esc-clock-frequency = <20000000>;
886 samsung,pll-clock-frequency = <24000000>;
892 compatible = "fsl,aips-bus", "simple-bus";
893 #address-cells = <1>;
894 #size-cells = <1>;
898 spba-bus@30800000 {
899 compatible = "fsl,spba-bus", "simple-bus";
900 #address-cells = <1>;
901 #size-cells = <1>;
906 #address-cells = <1>;
907 #size-cells = <0>;
908 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
913 clock-names = "ipg", "per";
914 dma-names = "rx", "tx";
920 #address-cells = <1>;
921 #size-cells = <0>;
922 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
927 clock-names = "ipg", "per";
928 dma-names = "rx", "tx";
934 #address-cells = <1>;
935 #size-cells = <0>;
936 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
941 clock-names = "ipg", "per";
942 dma-names = "rx", "tx";
948 compatible = "fsl,imx7d-uart",
949 "fsl,imx6q-uart";
954 clock-names = "ipg", "per";
959 compatible = "fsl,imx7d-uart",
960 "fsl,imx6q-uart";
965 clock-names = "ipg", "per";
970 compatible = "fsl,imx7d-uart",
971 "fsl,imx6q-uart";
976 clock-names = "ipg", "per";
981 #sound-dai-cells = <0>;
982 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
989 clock-names = "bus", "mclk1", "mclk2", "mclk3";
990 dma-names = "rx", "tx";
996 #sound-dai-cells = <0>;
997 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1004 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1005 dma-names = "rx", "tx";
1011 #sound-dai-cells = <0>;
1012 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1019 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1020 dma-names = "rx", "tx";
1027 compatible = "fsl,sec-v4.0";
1028 #address-cells = <1>;
1029 #size-cells = <1>;
1035 clock-names = "ipg", "aclk";
1038 compatible = "fsl,sec-v4.0-job-ring";
1044 compatible = "fsl,sec-v4.0-job-ring";
1050 compatible = "fsl,sec-v4.0-job-ring";
1057 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1062 clock-names = "ipg", "per";
1063 fsl,stop-mode = <&gpr 0x10 1>;
1068 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1073 clock-names = "ipg", "per";
1074 fsl,stop-mode = <&gpr 0x10 2>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1119 compatible = "fsl,imx7d-uart",
1120 "fsl,imx6q-uart";
1125 clock-names = "ipg", "per";
1130 compatible = "fsl,imx7d-uart",
1131 "fsl,imx6q-uart";
1136 clock-names = "ipg", "per";
1141 compatible = "fsl,imx7d-uart",
1142 "fsl,imx6q-uart";
1147 clock-names = "ipg", "per";
1152 compatible = "fsl,imx7d-uart",
1153 "fsl,imx6q-uart";
1158 clock-names = "ipg", "per";
1163 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1167 #mbox-cells = <2>;
1172 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1176 #mbox-cells = <2>;
1177 fsl,mu-side-b;
1182 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1188 phy-clkgate-delay-us = <400>;
1193 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1201 phy-clkgate-delay-us = <400>;
1206 #index-cells = <1>;
1207 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1212 #index-cells = <1>;
1213 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1218 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1224 clock-names = "ipg", "ahb", "per";
1225 bus-width = <4>;
1226 fsl,tuning-step = <2>;
1227 fsl,tuning-start-tap = <20>;
1232 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1238 clock-names = "ipg", "ahb", "per";
1239 bus-width = <4>;
1240 fsl,tuning-step = <2>;
1241 fsl,tuning-start-tap = <20>;
1246 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1252 clock-names = "ipg", "ahb", "per";
1253 bus-width = <4>;
1254 fsl,tuning-step = <2>;
1255 fsl,tuning-start-tap = <20>;
1260 compatible = "fsl,imx7d-qspi";
1262 reg-names = "QuadSPI", "QuadSPI-memory";
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1268 clock-names = "qspi_en", "qspi";
1272 sdma: dma-controller@30bd0000 {
1273 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1278 clock-names = "ipg", "ahb";
1279 #dma-cells = <3>;
1280 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1284 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1286 interrupt-names = "int0", "int1", "int2", "pps";
1296 clock-names = "ipg", "ahb", "ptp",
1298 fsl,num-tx-queues = <3>;
1299 fsl,num-rx-queues = <3>;
1300 fsl,stop-mode = <&gpr 0x10 3>;
1305 dma_apbh: dma-controller@33000000 {
1306 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1312 #dma-cells = <1>;
1313 dma-channels = <4>;
1317 gpmi: nand-controller@33002000 {
1318 compatible = "fsl,imx7d-gpmi-nand";
1319 #address-cells = <1>;
1320 #size-cells = <0>;
1322 reg-names = "gpmi-nand", "bch";
1324 interrupt-names = "bch";
1327 clock-names = "gpmi_io", "gpmi_bch_apb";
1329 dma-names = "rx-tx";
1331 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1332 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;