Lines Matching full:clks
77 clocks = <&clks IMX7D_CLK_ARM>;
114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
192 clocks = <&clks IMX7D_OCRAM_CLK>;
198 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
229 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
244 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
279 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
302 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
436 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
443 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
451 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
459 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
473 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
474 <&clks IMX7D_GPT1_ROOT_CLK>;
482 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
483 <&clks IMX7D_GPT2_ROOT_CLK>;
492 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
493 <&clks IMX7D_GPT3_ROOT_CLK>;
502 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
503 <&clks IMX7D_GPT4_ROOT_CLK>;
512 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
567 clocks = <&clks IMX7D_OCOTP_CLK>;
620 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
635 clocks = <&clks IMX7D_SNVS_CLK>;
643 clocks = <&clks IMX7D_SNVS_CLK>;
651 clks: clock-controller@30380000 { label
712 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
722 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
734 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
735 <&clks IMX7D_ECSPI4_ROOT_CLK>;
749 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
750 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
751 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
752 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
763 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
764 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
765 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
766 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
774 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
775 <&clks IMX7D_PWM1_ROOT_CLK>;
785 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
786 <&clks IMX7D_PWM2_ROOT_CLK>;
796 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
797 <&clks IMX7D_PWM3_ROOT_CLK>;
807 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
808 <&clks IMX7D_PWM4_ROOT_CLK>;
818 clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
833 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
834 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
843 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
844 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
845 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
875 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
876 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
878 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
879 <&clks IMX7D_PLL_SYS_PFD5_CLK>;
880 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
911 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
912 <&clks IMX7D_ECSPI1_ROOT_CLK>;
925 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
926 <&clks IMX7D_ECSPI2_ROOT_CLK>;
939 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
940 <&clks IMX7D_ECSPI3_ROOT_CLK>;
952 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
953 <&clks IMX7D_UART1_ROOT_CLK>;
963 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
964 <&clks IMX7D_UART2_ROOT_CLK>;
974 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
975 <&clks IMX7D_UART3_ROOT_CLK>;
985 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
986 <&clks IMX7D_SAI1_ROOT_CLK>,
987 <&clks IMX7D_CLK_DUMMY>,
988 <&clks IMX7D_CLK_DUMMY>;
1000 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
1001 <&clks IMX7D_SAI2_ROOT_CLK>,
1002 <&clks IMX7D_CLK_DUMMY>,
1003 <&clks IMX7D_CLK_DUMMY>;
1015 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
1016 <&clks IMX7D_SAI3_ROOT_CLK>,
1017 <&clks IMX7D_CLK_DUMMY>,
1018 <&clks IMX7D_CLK_DUMMY>;
1033 clocks = <&clks IMX7D_CAAM_CLK>,
1034 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1060 clocks = <&clks IMX7D_CLK_DUMMY>,
1061 <&clks IMX7D_CAN1_ROOT_CLK>;
1071 clocks = <&clks IMX7D_CLK_DUMMY>,
1072 <&clks IMX7D_CAN2_ROOT_CLK>;
1084 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1094 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1104 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1114 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1123 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1124 <&clks IMX7D_UART4_ROOT_CLK>;
1134 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1135 <&clks IMX7D_UART5_ROOT_CLK>;
1145 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1146 <&clks IMX7D_UART6_ROOT_CLK>;
1156 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1157 <&clks IMX7D_UART7_ROOT_CLK>;
1166 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1175 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1185 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1196 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1221 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1222 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1223 <&clks IMX7D_USDHC1_ROOT_CLK>;
1235 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1236 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1237 <&clks IMX7D_USDHC2_ROOT_CLK>;
1249 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1250 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1251 <&clks IMX7D_USDHC3_ROOT_CLK>;
1266 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1267 <&clks IMX7D_QSPI_ROOT_CLK>;
1276 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1277 <&clks IMX7D_SDMA_CORE_CLK>;
1291 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1292 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1293 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1294 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1295 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1314 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1325 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1326 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1331 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1332 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;