Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
20 #include <dt-bindings/thermal/thermal.h>
25 #address-cells = <1>;
26 #size-cells = <1>;
27 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a7";
36 reg = <0x0>;
38 clock-names = "cpu";
39 operating-points-v2 = <&cpu_opp_table>;
40 #cooling-cells = <2>; /* min followed by max */
44 cpu_opp_table: opp-table {
45 compatible = "operating-points-v2";
47 opp-90000000 {
48 opp-hz = /bits/ 64 <90000000>;
49 opp-microvolt = <1050000 1050000 1225000>;
50 clock-latency-ns = <320000>;
53 opp-250000000 {
54 opp-hz = /bits/ 64 <250000000>;
55 opp-microvolt = <1050000 1050000 1225000>;
56 clock-latency-ns = <320000>;
59 opp-600000000 {
60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <1050000 1050000 1225000>;
62 clock-latency-ns = <320000>;
63 opp-suspend;
66 opp-800000000 {
67 opp-hz = /bits/ 64 <800000000>;
68 opp-microvolt = <1150000 1125000 1225000>;
69 clock-latency-ns = <320000>;
72 opp-1000000002 {
73 opp-hz = /bits/ 64 <1000000002>;
74 opp-microvolt = <1250000 1225000 1300000>;
75 clock-latency-ns = <320000>;
79 thermal-zones {
80 cpu_thermal: cpu-thermal {
81 polling-delay-passive = <1000>;
82 polling-delay = <5000>;
83 thermal-sensors = <&thermal_sensor>;
86 cpu_normal: cpu-alert0 {
92 cpu_hot: cpu-alert1 {
98 cpu_critical: cpu-critical {
105 cooling-maps {
108 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
113 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 clock-frequency = <48000000>;
137 vddout25: fixed-regulator-vddout25 {
138 compatible = "regulator-fixed";
140 regulator-name = "VDDOUT25";
141 regulator-min-microvolt = <2500000>;
142 regulator-max-microvolt = <2500000>;
143 regulator-boot-on;
148 compatible = "mmio-sram";
149 #address-cells = <1>;
150 #size-cells = <1>;
151 reg = <0x100000 0x20000>;
155 thermal_sensor: thermal-sensor {
156 compatible = "generic-adc-thermal";
157 #thermal-sensor-cells = <0>;
158 io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>;
159 io-channel-names = "sensor-channel";
163 compatible = "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
169 compatible = "mmio-sram";
170 no-memory-wc;
171 reg = <0x00600000 0x2400>;
172 #address-cells = <1>;
173 #size-cells = <1>;
177 nfc_io: nfc-io@10000000 {
178 compatible = "atmel,sama5d3-nfc-io", "syscon";
179 reg = <0x10000000 0x8000000>;
183 compatible = "atmel,sama5d3-ebi";
184 #address-cells = <2>;
185 #size-cells = <1>;
187 reg = <0x40000000 0x20000000>;
195 nand_controller: nand-controller {
196 compatible = "atmel,sama5d3-nand-controller";
197 atmel,nfc-sram = <&nfc_sram>;
198 atmel,nfc-io = <&nfc_io>;
199 ecc-engine = <&pmecc>;
200 #address-cells = <2>;
201 #size-cells = <1>;
208 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
209 reg = <0xe0000000 0x4000>;
211 #address-cells = <1>;
212 #size-cells = <1>;
214 no-memory-wc;
218 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
219 reg = <0xe0004000 0x4000>;
220 gpio-controller;
221 #gpio-cells = <2>;
225 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
226 reg = <0xe0008000 0x20>;
230 compatible = "microchip,sama7g5-pinctrl";
231 reg = <0xe0014000 0x800>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 gpio-controller;
240 #gpio-cells = <2>;
244 pmc: clock-controller@e0018000 {
245 compatible = "microchip,sama7g5-pmc", "syscon";
246 reg = <0xe0018000 0x200>;
248 #clock-cells = <2>;
250 clock-names = "td_slck", "md_slck", "main_xtal";
253 reset_controller: reset-controller@e001d000 {
254 compatible = "microchip,sama7g5-rstc";
255 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
256 #reset-cells = <1>;
261 compatible = "microchip,sama7g5-shdwc", "syscon";
262 reg = <0xe001d010 0x10>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 atmel,wakeup-rtc-timer;
267 atmel,wakeup-rtt-timer;
272 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
273 reg = <0xe001d020 0x30>;
278 clk32k: clock-controller@e001d050 {
279 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
280 reg = <0xe001d050 0x4>;
282 #clock-cells = <1>;
286 compatible = "microchip,sama7g5-gpbr", "syscon";
287 reg = <0xe001d060 0x48>;
291 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
292 reg = <0xe001d0a8 0x30>;
298 compatible = "microchip,sama7g5-wdt";
299 reg = <0xe001d180 0x24>;
305 compatible = "microchip,sama7g5-chipid";
306 reg = <0xe0020000 0x8>;
310 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <0xe0800000 0x100>;
316 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
320 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
321 reg = <0xe0808000 0x1000>;
324 #address-cells = <1>;
325 #size-cells = <1>;
328 pmecc: ecc-engine@e0808070 {
329 compatible = "atmel,sama5d2-pmecc";
330 reg = <0xe0808070 0x490>,
336 compatible = "microchip,sama7g5-ospi";
337 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
338 reg-names = "qspi_base", "qspi_mmap";
342 dma-names = "tx", "rx";
344 clock-names = "pclk", "gclk";
345 #address-cells = <1>;
346 #size-cells = <0>;
351 compatible = "microchip,sama7g5-qspi";
352 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
353 reg-names = "qspi_base", "qspi_mmap";
357 dma-names = "tx", "rx";
359 clock-names = "pclk", "gclk";
360 #address-cells = <1>;
361 #size-cells = <0>;
367 reg = <0xe0828000 0x100>, <0x100000 0x7800>;
368 reg-names = "m_can", "message_ram";
371 interrupt-names = "int0", "int1";
373 clock-names = "hclk", "cclk";
374 assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
375 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
376 assigned-clock-rates = <40000000>;
377 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
383 reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
384 reg-names = "m_can", "message_ram";
387 interrupt-names = "int0", "int1";
389 clock-names = "hclk", "cclk";
390 assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
391 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
392 assigned-clock-rates = <40000000>;
393 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
399 reg = <0xe0830000 0x100>, <0x100000 0x10000>;
400 reg-names = "m_can", "message_ram";
403 interrupt-names = "int0", "int1";
405 clock-names = "hclk", "cclk";
406 assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
407 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
408 assigned-clock-rates = <40000000>;
409 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
415 reg = <0xe0834000 0x100>, <0x110000 0x4400>;
416 reg-names = "m_can", "message_ram";
419 interrupt-names = "int0", "int1";
421 clock-names = "hclk", "cclk";
422 assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
423 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
424 assigned-clock-rates = <40000000>;
425 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
431 reg = <0xe0838000 0x100>, <0x110000 0x8800>;
432 reg-names = "m_can", "message_ram";
435 interrupt-names = "int0", "int1";
437 clock-names = "hclk", "cclk";
438 assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
439 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
440 assigned-clock-rates = <40000000>;
441 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
447 reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
448 reg-names = "m_can", "message_ram";
451 interrupt-names = "int0", "int1";
453 clock-names = "hclk", "cclk";
454 assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
455 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
456 assigned-clock-rates = <40000000>;
457 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
462 compatible = "microchip,sama7g5-adc";
463 reg = <0xe1000000 0x200>;
466 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
467 assigned-clock-rates = <100000000>;
468 clock-names = "adc_clk";
470 dma-names = "rx";
471 atmel,min-sample-rate-hz = <200000>;
472 atmel,max-sample-rate-hz = <20000000>;
473 atmel,startup-time-ms = <4>;
474 #io-channel-cells = <1>;
475 nvmem-cells = <&temperature_calib>;
476 nvmem-cell-names = "temperature_calib";
481 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
482 reg = <0xe1204000 0x4000>;
485 clock-names = "hclock", "multclk";
486 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
487 assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
488 assigned-clock-rates = <200000000>;
489 microchip,sdcal-inverted;
494 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
495 reg = <0xe1208000 0x4000>;
498 clock-names = "hclock", "multclk";
499 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
500 assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
501 assigned-clock-rates = <200000000>;
502 microchip,sdcal-inverted;
507 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
508 reg = <0xe120c000 0x4000>;
511 clock-names = "hclock", "multclk";
512 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
513 assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
514 assigned-clock-rates = <200000000>;
515 microchip,sdcal-inverted;
520 compatible = "microchip,sama7g5-csi2dc";
521 reg = <0xe1404000 0x500>;
523 clock-names = "pclk", "scck";
524 assigned-clocks = <&xisc>;
525 assigned-clock-rates = <266000000>;
529 #address-cells = <1>;
530 #size-cells = <0>;
532 reg = <0>;
538 reg = <1>;
540 bus-width = <14>;
541 hsync-active = <1>;
542 vsync-active = <1>;
543 remote-endpoint = <&xisc_in>;
550 compatible = "microchip,sama7g5-isc";
551 reg = <0xe1408000 0x2000>;
554 clock-names = "hclock";
555 #clock-cells = <0>;
556 clock-output-names = "isc-mck";
561 bus-type = <5>; /* Parallel */
562 bus-width = <14>;
563 hsync-active = <1>;
564 vsync-active = <1>;
565 remote-endpoint = <&csi2dc_out>;
571 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
572 reg = <0xe1604000 0x4000>;
574 #pwm-cells = <3>;
580 compatible = "microchip,sama7g5-pdmc";
581 reg = <0xe1608000 0x1000>;
583 #sound-dai-cells = <0>;
585 dma-names = "rx";
587 clock-names = "pclk", "gclk";
592 compatible = "microchip,sama7g5-pdmc";
593 reg = <0xe160c000 0x1000>;
595 #sound-dai-cells = <0>;
597 dma-names = "rx";
599 clock-names = "pclk", "gclk";
604 #sound-dai-cells = <0>;
605 compatible = "microchip,sama7g5-spdifrx";
606 reg = <0xe1614000 0x4000>;
609 dma-names = "rx";
611 clock-names = "pclk", "gclk";
616 #sound-dai-cells = <0>;
617 compatible = "microchip,sama7g5-spdiftx";
618 reg = <0xe1618000 0x4000>;
621 dma-names = "tx";
623 clock-names = "pclk", "gclk";
627 compatible = "microchip,sama7g5-i2smcc";
628 #sound-dai-cells = <0>;
629 reg = <0xe161c000 0x4000>;
632 dma-names = "tx", "rx";
634 clock-names = "pclk", "gclk";
639 compatible = "microchip,sama7g5-i2smcc";
640 #sound-dai-cells = <0>;
641 reg = <0xe1620000 0x4000>;
644 dma-names = "tx", "rx";
646 clock-names = "pclk", "gclk";
650 eic: interrupt-controller@e1628000 {
651 compatible = "microchip,sama7g5-eic";
652 reg = <0xe1628000 0xec>;
653 interrupt-parent = <&gic>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
659 clock-names = "pclk";
664 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
665 reg = <0xe1800000 0x4000>;
668 clock-names = "pclk", "gclk";
672 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
673 reg = <0xe1804000 0x4000>;
676 clock-names = "pclk", "gclk";
680 compatible = "atmel,at91sam9g46-aes";
681 reg = <0xe1810000 0x100>;
684 clock-names = "aes_clk";
687 dma-names = "tx", "rx";
691 compatible = "atmel,at91sam9g46-sha";
692 reg = <0xe1814000 0x100>;
695 clock-names = "sha_clk";
697 dma-names = "tx";
701 compatible = "atmel,sama5d2-flexcom";
702 reg = <0xe1818000 0x200>;
704 #address-cells = <1>;
705 #size-cells = <1>;
710 compatible = "atmel,at91sam9260-usart";
711 reg = <0x200 0x200>;
712 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
715 clock-names = "usart";
718 dma-names = "tx", "rx";
719 atmel,use-dma-rx;
720 atmel,use-dma-tx;
726 compatible = "atmel,sama5d2-flexcom";
727 reg = <0xe181c000 0x200>;
729 #address-cells = <1>;
730 #size-cells = <1>;
735 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
736 reg = <0x600 0x200>;
738 #address-cells = <1>;
739 #size-cells = <0>;
741 atmel,fifo-size = <32>;
744 dma-names = "tx", "rx";
750 compatible = "atmel,sama5d2-flexcom";
751 reg = <0xe1824000 0x200>;
753 #address-cells = <1>;
754 #size-cells = <1>;
759 compatible = "atmel,at91sam9260-usart";
760 reg = <0x200 0x200>;
761 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
764 clock-names = "usart";
767 dma-names = "tx", "rx";
768 atmel,use-dma-rx;
769 atmel,use-dma-tx;
775 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
776 reg = <0xe2010000 0x100>;
783 compatible = "atmel,at91sam9g46-tdes";
784 reg = <0xe2014000 0x100>;
787 clock-names = "tdes_clk";
790 dma-names = "tx", "rx";
794 compatible = "atmel,sama5d2-flexcom";
795 reg = <0xe2018000 0x200>;
797 #address-cells = <1>;
798 #size-cells = <1>;
803 compatible = "atmel,at91sam9260-usart";
804 reg = <0x200 0x200>;
805 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
808 clock-names = "usart";
811 dma-names = "tx", "rx";
812 atmel,use-dma-rx;
813 atmel,use-dma-tx;
814 atmel,fifo-size = <16>;
820 compatible = "atmel,sama5d2-flexcom";
821 reg = <0xe2024000 0x200>;
823 #address-cells = <1>;
824 #size-cells = <1>;
829 compatible = "atmel,at91sam9260-usart";
830 reg = <0x200 0x200>;
831 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
834 clock-names = "usart";
837 dma-names = "tx", "rx";
838 atmel,use-dma-rx;
839 atmel,use-dma-tx;
840 atmel,fifo-size = <16>;
846 compatible = "microchip,sama7g5-gem";
847 reg = <0xe2800000 0x1000>;
855 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
856 assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
857 assigned-clock-rates = <125000000>;
862 compatible = "microchip,sama7g5-emac";
863 reg = <0xe2804000 0x1000>;
867 clock-names = "pclk", "hclk";
871 dma0: dma-controller@e2808000 {
872 compatible = "microchip,sama7g5-dma";
873 reg = <0xe2808000 0x1000>;
875 #dma-cells = <1>;
877 clock-names = "dma_clk";
881 dma1: dma-controller@e280c000 {
882 compatible = "microchip,sama7g5-dma";
883 reg = <0xe280c000 0x1000>;
885 #dma-cells = <1>;
887 clock-names = "dma_clk";
892 dma2: dma-controller@e1200000 {
893 compatible = "microchip,sama7g5-dma";
894 reg = <0xe1200000 0x1000>;
896 #dma-cells = <1>;
898 clock-names = "dma_clk";
899 dma-requests = <0>;
904 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
905 #address-cells = <1>;
906 #size-cells = <0>;
907 reg = <0xe2814000 0x100>;
910 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
914 compatible = "atmel,sama5d2-flexcom";
915 reg = <0xe2818000 0x200>;
917 #address-cells = <1>;
918 #size-cells = <1>;
923 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
924 reg = <0x600 0x200>;
926 #address-cells = <1>;
927 #size-cells = <0>;
929 atmel,fifo-size = <32>;
932 dma-names = "tx", "rx";
938 compatible = "atmel,sama5d2-flexcom";
939 reg = <0xe281c000 0x200>;
941 #address-cells = <1>;
942 #size-cells = <1>;
947 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
948 reg = <0x600 0x200>;
950 #address-cells = <1>;
951 #size-cells = <0>;
953 atmel,fifo-size = <32>;
956 dma-names = "tx", "rx";
962 compatible = "atmel,sama5d2-flexcom";
963 reg = <0xe2824000 0x200>;
965 #address-cells = <1>;
966 #size-cells = <1>;
971 compatible = "atmel,at91rm9200-spi";
972 reg = <0x400 0x200>;
975 clock-names = "spi_clk";
976 #address-cells = <1>;
977 #size-cells = <0>;
978 atmel,fifo-size = <32>;
981 dma-names = "tx", "rx";
987 compatible = "microchip,sama7g5-uddrc";
988 reg = <0xe3800000 0x4000>;
992 compatible = "microchip,sama7g5-ddr3phy";
993 reg = <0xe3804000 0x1000>;
997 compatible = "microchip,sama7g5-otpc", "syscon";
998 reg = <0xe8c00000 0x100>;
999 #address-cells = <1>;
1000 #size-cells = <1>;
1003 reg = <OTP_PKT(1) 76>;
1007 gic: interrupt-controller@e8c11000 {
1008 compatible = "arm,cortex-a7-gic";
1009 #interrupt-cells = <3>;
1010 #address-cells = <0>;
1011 interrupt-controller;
1012 reg = <0xe8c11000 0x1000>,