Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
89 compatible = "arm,cortex-a15";
90 reg = <0>;
94 compatible = "arm,cortex-a15";
95 reg = <1>;
99 compatible = "arm,cortex-a15";
100 reg = <2>;
104 compatible = "arm,cortex-a15";
105 reg = <3>;
109 compatible = "arm,cortex-a15";
110 reg = <0x100>;
114 compatible = "arm,cortex-a15";
115 reg = <0x101>;
119 compatible = "arm,cortex-a15";
120 reg = <0x102>;
124 compatible = "arm,cortex-a15";
125 reg = <0x103>;
129 compatible = "arm,cortex-a15";
130 reg = <0x200>;
134 compatible = "arm,cortex-a15";
135 reg = <0x201>;
139 compatible = "arm,cortex-a15";
140 reg = <0x202>;
144 compatible = "arm,cortex-a15";
145 reg = <0x203>;
149 compatible = "arm,cortex-a15";
150 reg = <0x300>;
154 compatible = "arm,cortex-a15";
155 reg = <0x301>;
159 compatible = "arm,cortex-a15";
160 reg = <0x302>;
164 compatible = "arm,cortex-a15";
165 reg = <0x303>;
170 compatible = "arm,armv7-timer";
171 interrupt-parent = <&gic>;
179 #clock-cells = <0>;
180 compatible = "fixed-clock";
181 clock-frequency = <50000000>;
185 #clock-cells = <0>;
186 compatible = "fixed-clock";
187 clock-frequency = <168000000>;
191 #clock-cells = <0>;
192 compatible = "fixed-clock";
193 clock-frequency = <375000000>;
197 /* It's a 32-bit SoC. */
198 #address-cells = <1>;
199 #size-cells = <1>;
200 compatible = "simple-bus";
201 interrupt-parent = <&gic>;
204 gic: interrupt-controller@c01000 {
205 compatible = "hisilicon,hip04-intc";
206 #interrupt-cells = <3>;
207 #address-cells = <0>;
208 interrupt-controller;
211 reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
217 reg = <0x3e00000 0x00100000>;
221 compatible = "hisilicon,hip04-fabric";
222 reg = <0x302a000 0x1000>;
227 reg = <0x3000000 0x1000>;
230 clock-names = "timer0clk", "timer1clk", "apb_pclk";
233 arm-pmu {
234 compatible = "arm,cortex-a15-pmu";
254 compatible = "snps,dw-apb-uart";
255 reg = <0x4007000 0x1000>;
258 clock-names = "baudclk", "apb_pclk";
259 reg-shift = <2>;
264 compatible = "hisilicon,hisi-ahci";
265 reg = <0xa000000 0x1000000>;
272 compatible = "arm,coresight-etb10", "arm,primecell";
273 reg = <0 0xe3c42000 0 0x1000>;
276 clock-names = "apb_pclk";
277 in-ports {
280 remote-endpoint = <&replicator0_out_port0>;
287 compatible = "arm,coresight-etb10", "arm,primecell";
288 reg = <0 0xe3c82000 0 0x1000>;
291 clock-names = "apb_pclk";
292 in-ports {
295 remote-endpoint = <&replicator1_out_port0>;
302 compatible = "arm,coresight-etb10", "arm,primecell";
303 reg = <0 0xe3cc2000 0 0x1000>;
306 clock-names = "apb_pclk";
307 in-ports {
310 remote-endpoint = <&replicator2_out_port0>;
317 compatible = "arm,coresight-etb10", "arm,primecell";
318 reg = <0 0xe3d02000 0 0x1000>;
321 clock-names = "apb_pclk";
322 in-ports {
325 remote-endpoint = <&replicator3_out_port0>;
332 compatible = "arm,coresight-tpiu", "arm,primecell";
333 reg = <0 0xe3c05000 0 0x1000>;
336 clock-names = "apb_pclk";
337 in-ports {
340 remote-endpoint = <&funnel4_out_port0>;
347 /* non-configurable replicators don't show up on the
350 compatible = "arm,coresight-static-replicator";
352 out-ports {
353 #address-cells = <1>;
354 #size-cells = <0>;
358 reg = <0>;
360 remote-endpoint = <&etb0_in_port>;
365 reg = <1>;
367 remote-endpoint = <&funnel4_in_port0>;
372 in-ports {
375 remote-endpoint = <&funnel0_out_port0>;
382 /* non-configurable replicators don't show up on the
385 compatible = "arm,coresight-static-replicator";
387 out-ports {
388 #address-cells = <1>;
389 #size-cells = <0>;
393 reg = <0>;
395 remote-endpoint = <&etb1_in_port>;
400 reg = <1>;
402 remote-endpoint = <&funnel4_in_port1>;
407 in-ports {
410 remote-endpoint = <&funnel1_out_port0>;
417 /* non-configurable replicators don't show up on the
420 compatible = "arm,coresight-static-replicator";
422 out-ports {
423 #address-cells = <1>;
424 #size-cells = <0>;
427 reg = <0>;
429 remote-endpoint = <&etb2_in_port>;
434 reg = <1>;
436 remote-endpoint = <&funnel4_in_port2>;
441 in-ports {
444 remote-endpoint = <&funnel2_out_port0>;
451 /* non-configurable replicators don't show up on the
454 compatible = "arm,coresight-static-replicator";
456 out-ports {
457 #address-cells = <1>;
458 #size-cells = <0>;
461 reg = <0>;
463 remote-endpoint = <&etb3_in_port>;
468 reg = <1>;
470 remote-endpoint = <&funnel4_in_port3>;
475 in-ports {
478 remote-endpoint = <&funnel3_out_port0>;
485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
486 reg = <0 0xe3c41000 0 0x1000>;
489 clock-names = "apb_pclk";
490 out-ports {
493 remote-endpoint =
499 in-ports {
500 #address-cells = <1>;
501 #size-cells = <0>;
504 reg = <0>;
506 remote-endpoint = <&ptm0_out_port>;
511 reg = <1>;
513 remote-endpoint = <&ptm1_out_port>;
518 reg = <2>;
520 remote-endpoint = <&ptm2_out_port>;
525 reg = <3>;
527 remote-endpoint = <&ptm3_out_port>;
534 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
535 reg = <0 0xe3c81000 0 0x1000>;
538 clock-names = "apb_pclk";
539 out-ports {
542 remote-endpoint =
548 in-ports {
549 #address-cells = <1>;
550 #size-cells = <0>;
553 reg = <0>;
555 remote-endpoint = <&ptm4_out_port>;
560 reg = <1>;
562 remote-endpoint = <&ptm5_out_port>;
567 reg = <2>;
569 remote-endpoint = <&ptm6_out_port>;
574 reg = <3>;
576 remote-endpoint = <&ptm7_out_port>;
583 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
584 reg = <0 0xe3cc1000 0 0x1000>;
587 clock-names = "apb_pclk";
588 out-ports {
591 remote-endpoint =
597 in-ports {
598 #address-cells = <1>;
599 #size-cells = <0>;
602 reg = <0>;
604 remote-endpoint = <&ptm8_out_port>;
609 reg = <1>;
611 remote-endpoint = <&ptm9_out_port>;
616 reg = <2>;
618 remote-endpoint = <&ptm10_out_port>;
623 reg = <3>;
625 remote-endpoint = <&ptm11_out_port>;
632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
633 reg = <0 0xe3d01000 0 0x1000>;
636 clock-names = "apb_pclk";
637 out-ports {
640 remote-endpoint =
646 in-ports {
647 #address-cells = <1>;
648 #size-cells = <0>;
651 reg = <0>;
653 remote-endpoint = <&ptm12_out_port>;
658 reg = <1>;
660 remote-endpoint = <&ptm13_out_port>;
665 reg = <2>;
667 remote-endpoint = <&ptm14_out_port>;
672 reg = <3>;
674 remote-endpoint = <&ptm15_out_port>;
681 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
682 reg = <0 0xe3c04000 0 0x1000>;
685 clock-names = "apb_pclk";
686 out-ports {
689 remote-endpoint = <&tpiu_in_port>;
694 in-ports {
695 #address-cells = <1>;
696 #size-cells = <0>;
699 reg = <0>;
701 remote-endpoint =
707 reg = <1>;
709 remote-endpoint =
715 reg = <2>;
717 remote-endpoint =
723 reg = <3>;
725 remote-endpoint =
733 compatible = "arm,coresight-etm3x", "arm,primecell";
734 reg = <0 0xe3c7c000 0 0x1000>;
737 clock-names = "apb_pclk";
739 out-ports {
742 remote-endpoint = <&funnel0_in_port0>;
749 compatible = "arm,coresight-etm3x", "arm,primecell";
750 reg = <0 0xe3c7d000 0 0x1000>;
753 clock-names = "apb_pclk";
755 out-ports {
758 remote-endpoint = <&funnel0_in_port1>;
765 compatible = "arm,coresight-etm3x", "arm,primecell";
766 reg = <0 0xe3c7e000 0 0x1000>;
769 clock-names = "apb_pclk";
771 out-ports {
774 remote-endpoint = <&funnel0_in_port2>;
781 compatible = "arm,coresight-etm3x", "arm,primecell";
782 reg = <0 0xe3c7f000 0 0x1000>;
785 clock-names = "apb_pclk";
787 out-ports {
790 remote-endpoint = <&funnel0_in_port3>;
797 compatible = "arm,coresight-etm3x", "arm,primecell";
798 reg = <0 0xe3cbc000 0 0x1000>;
801 clock-names = "apb_pclk";
803 out-ports {
806 remote-endpoint = <&funnel1_in_port0>;
813 compatible = "arm,coresight-etm3x", "arm,primecell";
814 reg = <0 0xe3cbd000 0 0x1000>;
817 clock-names = "apb_pclk";
819 out-ports {
822 remote-endpoint = <&funnel1_in_port1>;
829 compatible = "arm,coresight-etm3x", "arm,primecell";
830 reg = <0 0xe3cbe000 0 0x1000>;
833 clock-names = "apb_pclk";
835 out-ports {
838 remote-endpoint = <&funnel1_in_port2>;
845 compatible = "arm,coresight-etm3x", "arm,primecell";
846 reg = <0 0xe3cbf000 0 0x1000>;
849 clock-names = "apb_pclk";
851 out-ports {
854 remote-endpoint = <&funnel1_in_port3>;
861 compatible = "arm,coresight-etm3x", "arm,primecell";
862 reg = <0 0xe3cfc000 0 0x1000>;
865 clock-names = "apb_pclk";
867 out-ports {
870 remote-endpoint = <&funnel2_in_port0>;
877 compatible = "arm,coresight-etm3x", "arm,primecell";
878 reg = <0 0xe3cfd000 0 0x1000>;
880 clock-names = "apb_pclk";
882 out-ports {
885 remote-endpoint = <&funnel2_in_port1>;
892 compatible = "arm,coresight-etm3x", "arm,primecell";
893 reg = <0 0xe3cfe000 0 0x1000>;
896 clock-names = "apb_pclk";
898 out-ports {
901 remote-endpoint = <&funnel2_in_port2>;
908 compatible = "arm,coresight-etm3x", "arm,primecell";
909 reg = <0 0xe3cff000 0 0x1000>;
912 clock-names = "apb_pclk";
914 out-ports {
917 remote-endpoint = <&funnel2_in_port3>;
924 compatible = "arm,coresight-etm3x", "arm,primecell";
925 reg = <0 0xe3d3c000 0 0x1000>;
928 clock-names = "apb_pclk";
930 out-ports {
933 remote-endpoint = <&funnel3_in_port0>;
940 compatible = "arm,coresight-etm3x", "arm,primecell";
941 reg = <0 0xe3d3d000 0 0x1000>;
944 clock-names = "apb_pclk";
946 out-ports {
949 remote-endpoint = <&funnel3_in_port1>;
956 compatible = "arm,coresight-etm3x", "arm,primecell";
957 reg = <0 0xe3d3e000 0 0x1000>;
960 clock-names = "apb_pclk";
962 out-ports {
965 remote-endpoint = <&funnel3_in_port2>;
972 compatible = "arm,coresight-etm3x", "arm,primecell";
973 reg = <0 0xe3d3f000 0 0x1000>;
976 clock-names = "apb_pclk";
978 out-ports {
981 remote-endpoint = <&funnel3_in_port3>;