Lines Matching full:errata

338 	  specific physical addresses or enable errata workarounds that may
517 	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
531 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
540 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
549 	bool "ARM errata: Stale prediction on replaced interworking branch"
565 	bool "ARM errata: Processor deadlock when a false hazard is created"
581 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
596 	bool "ARM errata: DMB operation may be faulty"
612 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
630 	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
641 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
653 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
669 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
684 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
695 	bool "ARM errata: no automatic Store Buffer drain"
706 	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
718 	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
732 	bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
743        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
753 	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
763 	bool "ARM errata: incorrect instructions may be executed from loop buffer"
772 	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
781 	  This workaround for all both errata involves setting bit[12] of the
786 	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
796 	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
805 	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
813 	bool "ARM errata: A17: DMB ST might fail to create order between stores"
822 	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
830 	  config option from the A12 erratum due to the way errata are checked
834 	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
840 	  config option from the A12 erratum due to the way errata are checked
863 	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
871 	  This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,