Lines Matching +full:cpu +full:- +full:centric
1 # SPDX-License-Identifier: GPL-2.0
152 The ARM series is a line of low-power-consumption RISC chip designs
154 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
155 manufactured, but legacy ARM-based PC hardware remains popular in
166 supported in LLD until version 14. The combined range is -/+ 256 MiB,
259 Patch phys-to-virt and virt-to-phys translation functions at
263 This can only be used with non-XIP MMU kernels where the base
309 bool "MMU-based Paged Memory Management Support"
312 Select if you want MMU-based virtualised addressing space
347 # This is sorted alphabetically by mach-* pathname. However, plat-*
349 # plat- suffix) or along side the corresponding mach-* source.
351 source "arch/arm/mach-actions/Kconfig"
353 source "arch/arm/mach-alpine/Kconfig"
355 source "arch/arm/mach-artpec/Kconfig"
357 source "arch/arm/mach-aspeed/Kconfig"
359 source "arch/arm/mach-at91/Kconfig"
361 source "arch/arm/mach-axxia/Kconfig"
363 source "arch/arm/mach-bcm/Kconfig"
365 source "arch/arm/mach-berlin/Kconfig"
367 source "arch/arm/mach-clps711x/Kconfig"
369 source "arch/arm/mach-davinci/Kconfig"
371 source "arch/arm/mach-digicolor/Kconfig"
373 source "arch/arm/mach-dove/Kconfig"
375 source "arch/arm/mach-ep93xx/Kconfig"
377 source "arch/arm/mach-exynos/Kconfig"
379 source "arch/arm/mach-footbridge/Kconfig"
381 source "arch/arm/mach-gemini/Kconfig"
383 source "arch/arm/mach-highbank/Kconfig"
385 source "arch/arm/mach-hisi/Kconfig"
387 source "arch/arm/mach-hpe/Kconfig"
389 source "arch/arm/mach-imx/Kconfig"
391 source "arch/arm/mach-ixp4xx/Kconfig"
393 source "arch/arm/mach-keystone/Kconfig"
395 source "arch/arm/mach-lpc32xx/Kconfig"
397 source "arch/arm/mach-mediatek/Kconfig"
399 source "arch/arm/mach-meson/Kconfig"
401 source "arch/arm/mach-milbeaut/Kconfig"
403 source "arch/arm/mach-mmp/Kconfig"
405 source "arch/arm/mach-mstar/Kconfig"
407 source "arch/arm/mach-mv78xx0/Kconfig"
409 source "arch/arm/mach-mvebu/Kconfig"
411 source "arch/arm/mach-mxs/Kconfig"
413 source "arch/arm/mach-nomadik/Kconfig"
415 source "arch/arm/mach-npcm/Kconfig"
417 source "arch/arm/mach-omap1/Kconfig"
419 source "arch/arm/mach-omap2/Kconfig"
421 source "arch/arm/mach-orion5x/Kconfig"
423 source "arch/arm/mach-pxa/Kconfig"
425 source "arch/arm/mach-qcom/Kconfig"
427 source "arch/arm/mach-realtek/Kconfig"
429 source "arch/arm/mach-rpc/Kconfig"
431 source "arch/arm/mach-rockchip/Kconfig"
433 source "arch/arm/mach-s3c/Kconfig"
435 source "arch/arm/mach-s5pv210/Kconfig"
437 source "arch/arm/mach-sa1100/Kconfig"
439 source "arch/arm/mach-shmobile/Kconfig"
441 source "arch/arm/mach-socfpga/Kconfig"
443 source "arch/arm/mach-spear/Kconfig"
445 source "arch/arm/mach-sti/Kconfig"
447 source "arch/arm/mach-stm32/Kconfig"
449 source "arch/arm/mach-sunxi/Kconfig"
451 source "arch/arm/mach-tegra/Kconfig"
453 source "arch/arm/mach-ux500/Kconfig"
455 source "arch/arm/mach-versatile/Kconfig"
457 source "arch/arm/mach-vt8500/Kconfig"
459 source "arch/arm/mach-zynq/Kconfig"
461 # ARMv7-M architecture
470 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
479 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
480 with a range of available cores like Cortex-M3/M4/M7.
510 running on a CPU that supports it.
513 source "arch/arm/Kconfig-nommu"
517 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
524 instructions. This sensitivity can result in a CPU hang scenario.
531 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
534 Executing a SWP instruction to read-only memory does not set bit 11
552 This option enables the workaround for the 430973 Cortex-A8
555 same virtual address, whether due to self-modifying code or virtual
556 to physical address re-mapping, Cortex-A8 does not recover from the
557 stale interworking branch prediction. This results in Cortex-A8
562 available in non-secure mode.
569 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
576 register may not be available in non-secure mode and thus is not
585 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
589 workaround disables the write-allocate mode for the L2 cache via the
591 may not be available in non-secure mode and thus is not available on
600 This option enables the workaround for the 742230 Cortex-A9
604 the diagnostic register of the Cortex-A9 which causes the DMB
607 register may not be available in non-secure mode and thus is not
616 This option enables the workaround for the 742231 Cortex-A9
618 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
621 replaced from one of the CPUs at the same time as another CPU is
623 register of the Cortex-A9 which reduces the linefill issuing
625 diagnostics register may not be available in non-secure mode and thus
634 This option enables the workaround for the 643719 Cortex-A9 (prior to
644 This option enables the workaround for the 720789 Cortex-A9 (prior to
657 This option enables the workaround for the 743622 Cortex-A9
659 optimisation in the Cortex-A9 Store Buffer may lead to data
661 register of the Cortex-A9 which disables the Store Buffer
665 may not be available in non-secure mode and thus is not available on a
673 This option enables the workaround for the 751472 Cortex-A9 (prior
676 operation is received by a CPU before the ICIALLUIS has completed,
679 not be available in non-secure mode and thus is not available on
687 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
690 can populate the micro-TLB with a stale entry which may be hit with
698 This option enables the workaround for the 754327 Cortex-A9 (prior to
706 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
711 hit-under-miss enabled). It sets the undocumented bit 31 in
713 register, thus disabling hit-under-miss without putting the
722 affecting Cortex-A9 MPCore with two or more processors (all
735 This option enables the workaround for the 764319 Cortex A-9 erratum.
746 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
753 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
756 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
766 This option enables the workaround for the 773022 Cortex-A15
776 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
778 - Cortex-A12 852422: Execution of a sequence of instructions might
779 lead to either a data corruption or a CPU deadlock. Not fixed in
780 any Cortex-A12 cores yet.
789 This option enables the workaround for the 821420 Cortex-A12
793 deadlock when the VMOV instructions are issued out-of-order.
799 This option enables the workaround for the 825619 Cortex-A12
802 and Device/Strongly-Ordered loads and stores might cause deadlock
805 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
808 This option enables the workaround for the 857271 Cortex-A12
809 (all revs) erratum. Under very rare timing conditions, the CPU might
816 This option enables the workaround for the 852421 Cortex-A17
826 - Cortex-A17 852423: Execution of a sequence of instructions might
827 lead to either a data corruption or a CPU deadlock. Not fixed in
828 any Cortex-A17 cores yet.
829 This is identical to Cortex-A12 erratum 852422. It is a separate
834 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
837 This option enables the workaround for the 857272 Cortex-A17 erratum.
839 This is identical to Cortex-A12 erratum 857271. It is a separate
853 name of a bus system, i.e. the way the CPU talks to the other stuff
871 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
881 This option should be selected by machines which have an SMP-
882 capable CPU.
884 The only effect of this option is to make the SMP-related
888 bool "Symmetric Multi-Processing"
894 This enables support for systems with more than one CPU. If you have
895 a system with only one CPU, say N. If you have a system with more
896 than one CPU, say Y.
898 If you say N here, the kernel will run on uni- and multiprocessor
899 machines, but will use only one CPU of a multiprocessor machine. If
904 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
905 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
906 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
915 SMP kernels contain instructions which fail on non-SMP processors.
933 bool "Support cpu topology definition"
937 Support ARM cpu topology definition. The MPIDR register defines
938 affinity between processors which is then used to describe the cpu
942 bool "Multi-core scheduler support"
945 Multi-core scheduler support improves the CPU scheduler's decision
946 making when dealing with multi-core CPU chips at a cost of slightly
953 Improves the CPU scheduler's decision making when dealing with
975 bool "Multi-Cluster Power Management"
979 for (multi-)cluster based systems, such as big.LITTLE based
1055 int "Maximum number of CPUs (2-32)"
1063 debugging is enabled, which uses half of the per-CPU fixmap
1067 bool "Support for hot-pluggable CPUs"
1072 can be controlled through /sys/devices/system/cpu.
1080 implementing the PSCI specification for CPU-centric power
1128 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1134 Thumb-2 mode.
1151 with the sdiv or udiv plus "bx lr" instructions when the CPU
1224 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1232 user-space 2nd level page tables to reside in high memory.
1235 bool "Enable use of CPU domains to implement privileged no-access"
1241 use-after-free bugs becoming an exploitable privilege escalation
1245 CPUs with low-vector mappings use a best-efforts implementation.
1268 Disabling this is usually safe for small single-platform
1292 address divisible by 4. On 32-bit ARM processors, these non-aligned
1295 correct operation of some network protocols. With an IP-only
1303 Implement faster copy_to_user and clear_user methods for CPU
1304 cores where a 8-word STM instruction give significantly higher
1311 However, if the CPU data cache is using a write-allocate mode,
1351 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1405 The physical address at which the ROM-able zImage is to be
1407 ROM-able zImage formats normally set this to a suitable
1417 for the ROM-able zImage which must be available while the
1420 Platforms which normally make use of ROM-able zImage formats
1472 Uses the command-line options passed by the boot loader instead of
1479 The command-line arguments provided by the boot loader will be
1490 architectures, you should supply some command-line options at build
1501 Uses the command-line options passed by the boot loader. If
1508 The command-line arguments provided by the boot loader will be
1517 command-line options your boot loader passes to the kernel.
1521 bool "Kernel Execute-In-Place from ROM"
1525 Execute-In-Place allows the kernel to run from non-volatile storage
1526 directly addressable by the CPU, such as NOR flash. This saves RAM
1528 to RAM. Read-write sections, such as the data section and stack,
1582 will be determined at run-time, either by masking the current IP
1600 by UEFI firmware (such as non-volatile variables, realtime
1615 continue to boot on existing non-UEFI platforms.
1621 to be enabled much earlier than we do on ARM, which is non-trivial.
1625 menu "CPU Power Management"
1644 your machine has an FPA or floating point co-processor podule.
1653 Say Y to include 80-bit support in the kernel floating-point
1654 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1655 Note that gcc does not generate 80-bit operations by default,
1668 It is very simple, and approximately 3-6 times faster than NWFPE.
1676 bool "VFP-format floating point maths"
1682 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for