boot/dts/vdk_axs10x_mb.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
10 		compatible = "simple-bus";
11 		#address-cells = <1>;
12 		#size-cells = <1>;
14 		interrupt-parent = <&mb_intc>;
18 				compatible = "fixed-clock";
19 				clock-frequency = <50000000>;
20 				#clock-cells = <0>;
24 				compatible = "fixed-clock";
25 				clock-frequency = <50000000>;
26 				#clock-cells = <0>;
30 				#clock-cells = <0>;
31 				compatible = "fixed-clock";
32 				clock-frequency = <25175000>;
37 			#interrupt-cells = <1>;
39 			reg = < 0x18000 0x2000 >;
41 			interrupt-names = "macirq";
42 			phy-mode = "rgmii";
43 			snps,phy-addr = < 0 >;  // VDK model phy address is 0
46 			clock-names = "stmmaceth";
50 			compatible = "generic-ehci";
51 			reg = < 0x40000 0x100 >;
56 			compatible = "snps,dw-apb-uart";
57 			reg = <0x20000 0x100>;
58 			clock-frequency = <2403200>;
61 			reg-shift = <2>;
62 			reg-io-width = <4>;
66 			compatible = "snps,dw-apb-uart";
67 			reg = <0x21000 0x100>;
68 			clock-frequency = <2403200>;
71 			reg-shift = <2>;
72 			reg-io-width = <4>;
76 			compatible = "snps,dw-apb-uart";
77 			reg = <0x22000 0x100>;
78 			clock-frequency = <2403200>;
81 			reg-shift = <2>;
82 			reg-io-width = <4>;
88 			reg = <0x17000 0x400>;
90 			clock-names = "pxlclk";
96 			reg = <0x17400 0x14>;
98 			interrupt-names = "arc_ps2_irq";
102 			compatible = "snps,dw-mshc";
103 			reg = <0x15000 0x400>;
104 			fifo-depth = <1024>;
105 			card-detect-delay = <200>;
107 			clock-names = "biu", "ciu";
109 			bus-width = <4>;
117 	 * it maps areas outside of MB's 0xez-0xfz.
120 		compatible = "generic-uio";
121 		reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>;
122 		reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
123 		interrupt-parent = <&mb_intc>;