alpha/lib/ev6-memset.S

23  * A future enhancement might be to put in a byte store loop for really
25  * a win in the kernel would depend upon the contextual usage.
48 	 * undertake a major re-write to interleave the constant materialization
61 	insbl	$1,3,$4		# U : 00000000ch000000
63 	or	$3,$4,$3	# E : 00000000chch0000
64 	inswl	$17,4,$5	# U : 0000chch00000000
70 	bic	$1,7,$1		# E : fit within a single quadword?
79 	 * Target address is misaligned, and won't fit within a quadword
81 	ldq_u $4,0($16)		# L : Fetch first partial
87 	mskql $4,$16,$4		# U : clear relevant parts of the quad
89 	bis $2,$4,$1		# E : Final bytes
96 .align 4
110 	 * Lifted a bunch of code from clear_user.S
113 	 * $5	A copy of $16
120 	subq	$3, 16, $4	# E : Only try to unroll if > 128 bytes
122 	blt	$4, loop_b	# U :
126 	 * through unrolled loop.  Do a quad at a time to get us 0mod64
139 	addq	$5, 8, $4	# E : Initial wh64 address (filler instruction)
151 	 * Scratch registers available: $7, $2, $4, $1
152 	 * we know that we'll be taking a minimum of one trip through
153  	 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
161 	wh64	($4)		# L1 : memory subsystem write hint
166 	addq	$5, 128, $4	# E : speculative target of next wh64
173 	cmovlt	$2, $7, $4	# E : Latency 2, extra mapping cycle
191 .align 4
211 	insqh $17,$6,$4		# U : New bits
212 	bis $2,$4,$1		# E : Put it all together
219 	mskql $1,$16,$4		# U : Clear old
220 	bis $2,$4,$2		# E : New result
222 	mskql $2,$6,$4		# U :
224 	bis $2,$4,$1		# E :
240 .align 4
251 	bic $1,7,$1		# E : fit within a single quadword
257 	 * Target address is misaligned, and won't fit within a quadword
259 	ldq_u $4,0($16)		# L : Fetch first partial
265 	mskql $4,$16,$4		# U : clear relevant parts of the quad
267 	bis $2,$4,$1		# E : Final bytes
274 .align 4
288 	 * Lifted a bunch of code from clear_user.S
291 	 * $5	A copy of $16
298 	subq	$3, 16, $4	# E : Only try to unroll if > 128 bytes
300 	blt	$4, loop	# U :
304 	 * through unrolled loop.  Do a quad at a time to get us 0mod64
317 	addq	$5, 8, $4	# E : Initial wh64 address (filler instruction)
329 	 * Scratch registers available: $7, $2, $4, $1
330 	 * we know that we'll be taking a minimum of one trip through
331  	 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
339 	wh64	($4)		# L1 : memory subsystem write hint
344 	addq	$5, 128, $4	# E : speculative target of next wh64
351 	cmovlt	$2, $7, $4	# E : Latency 2, extra mapping cycle
369 .align 4
389 	insqh $17,$6,$4		# U : New bits
390 	bis $2,$4,$1		# E : Put it all together
397 	mskql $1,$16,$4		# U : Clear old
398 	bis $2,$4,$2		# E : New result
400 	mskql $2,$6,$4		# U :
402 	bis $2,$4,$1		# E :
414 	 * This is a replicant of the __constant_c_memset code, rescheduled
430 	inswl	$17,4,$3	# U : 0000c1c200000000
431 	inswl	$17,6,$4	# U : c1c2000000000000
435 	or	$3,$4,$17	# E : c1c2c1c200000000
436 	bic	$1,7,$1		# E : fit within a single quadword
445 	 * Target address is misaligned, and won't fit within a quadword
447 	ldq_u $4,0($16)		# L : Fetch first partial
453 	mskql $4,$16,$4		# U : clear relevant parts of the quad
455 	bis $2,$4,$1		# E : Final bytes
462 .align 4
476 	 * Lifted a bunch of code from clear_user.S
479 	 * $5	A copy of $16
486 	subq	$3, 16, $4	# E : Only try to unroll if > 128 bytes
488 	blt	$4, loop_w	# U :
492 	 * through unrolled loop.  Do a quad at a time to get us 0mod64
505 	addq	$5, 8, $4	# E : Initial wh64 address (filler instruction)
517 	 * Scratch registers available: $7, $2, $4, $1
518 	 * we know that we'll be taking a minimum of one trip through
519  	 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
527 	wh64	($4)		# L1 : memory subsystem write hint
532 	addq	$5, 128, $4	# E : speculative target of next wh64
539 	cmovlt	$2, $7, $4	# E : Latency 2, extra mapping cycle
557 .align 4
577 	insqh $17,$6,$4		# U : New bits
578 	bis $2,$4,$1		# E : Put it all together
585 	mskql $1,$16,$4		# U : Clear old
586 	bis $2,$4,$2		# E : New result
588 	mskql $2,$6,$4		# U :
590 	bis $2,$4,$1		# E :