39 	/* Note mask bit is true for DISABLED irqs.  */
42 	void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 	void (*ack_irq_hw)(unsigned long bit);
64  * Bit      Meaning               Kernel IRQ
68  * 2        TULIP (builtin)		32
93 sable_update_irq_hw(unsigned long bit, unsigned long mask)  in sable_update_irq_hw()  argument
97 	if (bit >= 16) {  in sable_update_irq_hw()
100 	} else if (bit >= 8) {  in sable_update_irq_hw()
109 sable_ack_irq_hw(unsigned long bit)  in sable_ack_irq_hw()  argument
113 	if (bit >= 16) {  in sable_ack_irq_hw()
115 		val1 = 0xE0 | (bit - 16);  in sable_ack_irq_hw()
117 	} else if (bit >= 8) {  in sable_ack_irq_hw()
119 		val1 = 0xE0 | (bit - 8);  in sable_ack_irq_hw()
123 		val1 = 0xE0 | (bit - 0);  in sable_ack_irq_hw()
143 		34, 33, 32, 12, 35, 36,  1,  6,	/* mask 0-7  */
187  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
200 		{ 32+0,  32+0,  32+0,  32+0,  32+0},  /* IdSel 0,  TULIP  */  in sable_map_irq()
201 		{ 32+1,  32+1,  32+1,  32+1,  32+1},  /* IdSel 1,  SCSI   */  in sable_map_irq()
206 		{ 32+2,  32+2,  32+2,  32+2,  32+2},  /* IdSel 6,  slot 0 */  in sable_map_irq()
207 		{ 32+3,  32+3,  32+3,  32+3,  32+3},  /* IdSel 7,  slot 1 */  in sable_map_irq()
208 		{ 32+4,  32+4,  32+4,  32+4,  32+4}   /* IdSel 8,  slot 2 */  in sable_map_irq()
223  * Bit      Meaning               Kernel IRQ
257  *32        PCI 0 slot 4 A primary bus  32
292 lynx_update_irq_hw(unsigned long bit, unsigned long mask)  in lynx_update_irq_hw()  argument
308 lynx_ack_irq_hw(unsigned long bit)  in lynx_ack_irq_hw()  argument
310 	*(vulp)T2_VAR = (u_long) bit;  in lynx_ack_irq_hw()
321 		32, 33, 34, 35, 36, 37, 38, 39,	/* mask 32-39 */
331 		32, 33, 34, 35, 36, 37, 38, 39,	/* mask 32-39 */
386 		{   32,    32,    33,    34,    35},  /* IdSel 17,  slot 4 */  in lynx_map_irq()
447 	unsigned long bit, mask;  in sable_lynx_enable_irq()  local
449 	bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];  in sable_lynx_enable_irq()
451 	mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);  in sable_lynx_enable_irq()
452 	sable_lynx_irq_swizzle->update_irq_hw(bit, mask);  in sable_lynx_enable_irq()
455 	printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",  in sable_lynx_enable_irq()
456 	       __func__, mask, bit, irq);  in sable_lynx_enable_irq()
463 	unsigned long bit, mask;  in sable_lynx_disable_irq()  local
465 	bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];  in sable_lynx_disable_irq()
467 	mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;  in sable_lynx_disable_irq()
468 	sable_lynx_irq_swizzle->update_irq_hw(bit, mask);  in sable_lynx_disable_irq()
471 	printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",  in sable_lynx_disable_irq()
472 	       __func__, mask, bit, irq);  in sable_lynx_disable_irq()
479 	unsigned long bit, mask;  in sable_lynx_mask_and_ack_irq()  local
481 	bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];  in sable_lynx_mask_and_ack_irq()
483 	mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;  in sable_lynx_mask_and_ack_irq()
484 	sable_lynx_irq_swizzle->update_irq_hw(bit, mask);  in sable_lynx_mask_and_ack_irq()
485 	sable_lynx_irq_swizzle->ack_irq_hw(bit);  in sable_lynx_mask_and_ack_irq()
503 	int bit, irq;  in sable_lynx_srm_device_interrupt()  local
505 	bit = (vector - 0x800) >> 4;  in sable_lynx_srm_device_interrupt()
506 	irq = sable_lynx_irq_swizzle->mask_to_irq[bit];  in sable_lynx_srm_device_interrupt()
508 	printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n",  in sable_lynx_srm_device_interrupt()
509 	       __func__, vector, bit, irq);  in sable_lynx_srm_device_interrupt()