Lines Matching +full:8 +full:- +full:cpu
1 // SPDX-License-Identifier: GPL-2.0
37 * By default, we direct-map starting at 2GB, in order to allow the
38 * maximum size direct-map window (2GB) to match the maximum amount of
40 * floppy to DMA only via the scatter/gather window set up for 8MB
41 * ISA DMA, since the maximum ISA DMA address is 2GB-1.
43 * For now, this seems a reasonable trade-off: even though most SABLEs
62 * NOTE: Herein lie back-to-back mb instructions. They are magic.
68 * BIOS32-style PCI interface:
108 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
111 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
114 * 10:8 Function number
120 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
121 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
123 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
126 * 23:16 bus number (8 bits = 128 possible buses)
128 * 10:8 function number
132 * The function number selects which function of a multi-function device
145 u8 bus = pbus->number; in mk_conf_addr()
156 if (device > 8) { in mk_conf_addr()
157 DBG(("mk_conf_addr: device (%d)>20, returning -1\n", in mk_conf_addr()
159 return -1; in mk_conf_addr()
163 addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where); in mk_conf_addr()
167 addr = (bus << 16) | (device_fn << 8) | (where); in mk_conf_addr()
183 unsigned int value, cpu, taken; in conf_read() local
186 cpu = smp_processor_id(); in conf_read()
199 mcheck_expected(cpu) = 1; in conf_read()
200 mcheck_taken(cpu) = 0; in conf_read()
201 t2_mcheck_any_expected |= (1 << cpu); in conf_read()
211 another CPU is in the midst of handling a real mcheck via in conf_read()
215 if ((taken = mcheck_taken(cpu))) { in conf_read()
216 mcheck_taken(cpu) = 0; in conf_read()
217 t2_mcheck_last_taken |= (1 << cpu); in conf_read()
221 mcheck_expected(cpu) = 0; in conf_read()
237 unsigned int cpu, taken; in conf_write() local
240 cpu = smp_processor_id(); in conf_write()
251 mcheck_expected(cpu) = 1; in conf_write()
252 mcheck_taken(cpu) = 0; in conf_write()
253 t2_mcheck_any_expected |= (1 << cpu); in conf_write()
263 this CPU is in the midst of handling a real mcheck via in conf_write()
267 if ((taken = mcheck_taken(cpu))) { in conf_write()
268 mcheck_taken(cpu) = 0; in conf_write()
269 t2_mcheck_last_taken |= (1 << cpu); in conf_write()
272 mcheck_expected(cpu) = 0; in conf_write()
295 mask = (size - 1) * 8; in t2_read_config()
296 shift = (where & 3) * 8; in t2_read_config()
313 mask = (size - 1) * 8; in t2_write_config()
315 conf_write(addr, value << ((where & 3) * 8), type1); in t2_write_config()
333 temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20); in t2_direct_map_window1()
335 temp = (length - 1) & 0xfff00000UL; in t2_direct_map_window1()
354 hose->sg_isa = iommu_arena_new(hose, base, length, SMP_CACHE_BYTES); in t2_sg_map_window2()
355 hose->sg_pci = NULL; in t2_sg_map_window2()
357 temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20); in t2_sg_map_window2()
359 temp = (length - 1) & 0xfff00000UL; in t2_sg_map_window2()
361 *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1; in t2_sg_map_window2()
364 t2_pci_tbi(hose, 0, -1); /* flush TLB all */ in t2_sg_map_window2()
436 hose->io_space = &ioport_resource; in t2_init_arch()
438 hae_mem->start = 0; in t2_init_arch()
439 hae_mem->end = T2_MEM_R1_MASK; in t2_init_arch()
440 hae_mem->name = pci_hae0_name; in t2_init_arch()
443 hose->mem_space = hae_mem; in t2_init_arch()
444 hose->index = 0; in t2_init_arch()
446 hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR; in t2_init_arch()
447 hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR; in t2_init_arch()
448 hose->sparse_io_base = T2_IO - IDENT_ADDR; in t2_init_arch()
449 hose->dense_io_base = 0; in t2_init_arch()
452 * Set up the PCI->physical memory translation windows. in t2_init_arch()
477 * Thus we can now run standard X servers on SABLE/LYNX. :-) in t2_init_arch()
526 t2_clear_errors(int cpu) in t2_clear_errors() argument
530 cpu_regs = (struct sable_cpu_csr *)T2_CPUn_BASE(cpu); in t2_clear_errors()
532 cpu_regs->sic &= ~SIC_SEIC; in t2_clear_errors()
534 /* Clear CPU errors. */ in t2_clear_errors()
535 cpu_regs->bcce |= cpu_regs->bcce; in t2_clear_errors()
536 cpu_regs->cbe |= cpu_regs->cbe; in t2_clear_errors()
537 cpu_regs->bcue |= cpu_regs->bcue; in t2_clear_errors()
538 cpu_regs->dter |= cpu_regs->dter; in t2_clear_errors()
549 * CPUs receive it. And, the issuing CPU, in the case of PCI Config
559 int cpu = smp_processor_id(); in t2_machine_check() local
568 t2_clear_errors(cpu); in t2_machine_check()
576 if (!mcheck_expected(cpu) && t2_mcheck_any_expected) { in t2_machine_check()
578 * FUNKY: Received mcheck on a CPU and not in t2_machine_check()
579 * expecting it, but another CPU is expecting one. in t2_machine_check()
581 * Just dismiss it for now on this CPU... in t2_machine_check()
585 printk("t2_machine_check(cpu%d): any_expected 0x%x -" in t2_machine_check()
586 " (assumed) spurious -" in t2_machine_check()
587 " code 0x%x\n", cpu, t2_mcheck_any_expected, in t2_machine_check()
588 (unsigned int)mchk_header->code); in t2_machine_check()
594 if (!mcheck_expected(cpu) && !t2_mcheck_any_expected) { in t2_machine_check()
595 if (t2_mcheck_last_taken & (1 << cpu)) { in t2_machine_check()
598 printk("t2_machine_check(cpu%d): last_taken 0x%x - " in t2_machine_check()
599 "unexpected mcheck - code 0x%x\n", in t2_machine_check()
600 cpu, t2_mcheck_last_taken, in t2_machine_check()
601 (unsigned int)mchk_header->code); in t2_machine_check()
615 printk("%s t2_mcheck(cpu%d): last_taken 0x%x - " in t2_machine_check()
616 "any_expected 0x%x - code 0x%x\n", in t2_machine_check()
617 (mcheck_expected(cpu) ? "EX" : "UN"), cpu, in t2_machine_check()
619 (unsigned int)mchk_header->code); in t2_machine_check()
623 process_mcheck_info(vector, la_ptr, "T2", mcheck_expected(cpu)); in t2_machine_check()