alpha/kernel/core_apecs.c

1 // SPDX-License-Identifier: GPL-2.0
8  * taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit
31  * NOTE: Herein lie back-to-back mb instructions.  They are magic.
37  * BIOS32-style PCI interface:
61  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
63  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
65  *	31:11	Device select bit.
73  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
75  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
84  *	The function number selects which function of a multi-function device
97 	u8 bus = pbus->number;  in mk_conf_addr()
109 			DBGC(("mk_conf_addr: device (%d) > 20, returning -1\n",  in mk_conf_addr()
111 			return -1;  in mk_conf_addr()
175 	 * then we can make this conditional on the type.  in conf_read()
245 	 * then we can make this conditional on the type.  in conf_write()
286 	mask = (size - 1) * 8;  in apecs_read_config()
304 	mask = (size - 1) * 8;  in apecs_write_config()
334 	hose->io_space = &ioport_resource;  in apecs_init_arch()
335 	hose->mem_space = &iomem_resource;  in apecs_init_arch()
336 	hose->index = 0;  in apecs_init_arch()
338 	hose->sparse_mem_base = APECS_SPARSE_MEM - IDENT_ADDR;  in apecs_init_arch()
339 	hose->dense_mem_base = APECS_DENSE_MEM - IDENT_ADDR;  in apecs_init_arch()
340 	hose->sparse_io_base = APECS_IO - IDENT_ADDR;  in apecs_init_arch()
341 	hose->dense_io_base = 0;  in apecs_init_arch()
347 	 * Window 2 is scatter-gather 8MB at 8MB (for isa)  in apecs_init_arch()
349 	hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000,  in apecs_init_arch()
351 	hose->sg_pci = NULL;  in apecs_init_arch()
356 	*(vuip)APECS_IOC_PM1R = (__direct_map_size - 1) & 0xfff00000U;  in apecs_init_arch()
359 	*(vuip)APECS_IOC_PB2R = hose->sg_isa->dma_base | 0x000c0000;  in apecs_init_arch()
360 	*(vuip)APECS_IOC_PM2R = (hose->sg_isa->size - 1) & 0xfff00000;  in apecs_init_arch()
361 	*(vuip)APECS_IOC_TB2R = virt_to_phys(hose->sg_isa->ptes) >> 1;  in apecs_init_arch()
363 	apecs_pci_tbi(hose, 0, -1);  in apecs_init_arch()
402 		(la_ptr + mchk_header->proc_offset  in apecs_machine_check()
403 		 - sizeof(mchk_procdata->paltemp));  in apecs_machine_check()
406 		(la_ptr + mchk_header->sys_offset);  in apecs_machine_check()
419 			     && (mchk_sysdata->epic_dcsr & 0x0c00UL)));  in apecs_machine_check()