Lines Matching +full:inverted +full:- +full:rx
1 .. SPDX-License-Identifier: GPL-2.0+
12 +--------------+----------+---------+
16 +--------------+----------+---------+
18 +--------------+----------+---------+
19 |Sub-vendor ID | `0x1AE0` | Google |
20 +--------------+----------+---------+
21 |Sub-device ID | `0x0058` | |
22 +--------------+----------+---------+
24 +--------------+----------+---------+
26 +--------------+----------+---------+
30 The gVNIC PCI device exposes three 32-bit memory BARS:
31 - Bar0 - Device configuration and status registers.
32 - Bar1 - MSI-X vector table
33 - Bar2 - IRQ, RX and TX doorbells
38 - Registers
39 - A block of MMIO registers
40 - See gve_register.h for more detail
41 - Admin Queue
42 - See description below
43 - Reset
44 - At any time the device can be reset
45 - Interrupts
46 - See supported interrupts below
47 - Transmit and Receive Queues
48 - See description below
51 ------------------
56 ------------------
58 QPL ("queue-page-list") mode communicates data through a set of
59 pre-registered pages.
65 ---------
72 ----------
73 - Admin Queue messages and registers are all Big Endian.
74 - GQI descriptors and datapath registers are Big Endian.
75 - DQO descriptors and datapath registers are Little Endian.
78 ----------------
95 -------------
101 ----------
121 ------------------
125 The descriptor rings are power-of-two-sized ring buffers consisting of
126 fixed-size descriptors. They advance their head pointer using a __be32
128 descriptors in-order and updating a __be32 counter. Both the doorbell
146 ------------------
147 - Every TX and RX queue is assigned a notification block.
149 - TX and RX buffers queues, which send descriptors to the device, use MMIO
152 - RX and TX completion queues, which receive descriptors from the device, use a
155 populate received descriptors with the "next generation" which is inverted
159 - It's the driver's responsibility to ensure that the RX and TX completion
163 - TX packets have a 16 bit completion_tag and RX buffers have a 16 bit
164 buffer_id. These will be returned on the TX completion and RX queues
174 The driver posts fixed sized buffers to HW on the RX buffer queue. The packet
175 received on the associated RX queue may span multiple descriptors.