Documentation/fpga/dfl.rst

2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
20 Device Feature List (DFL) Overview
22 Device Feature List (DFL) defines a linked list of feature headers within the
32  +----------+  |   | Feature  |  |   | Feature  |  |   | Feature  |
38  +----------+  |   | Feature  |      | Feature  |      | Feature  |
66 Feature Header (Next_DFH) pointer.
68 Each FIU, AFU and Private Feature could implement its own functional registers.
70 e.g. FME Header Register Set, and the one for Private Feature, is named as
71 Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
73 This Device Feature List provides a way of linking features together, it's
74 convenient for software to locate each feature by walking through this list,
78 Device Feature Header - Version 0
80 Version 0 (DFHv0) is the original version of the Device Feature Header.
94   * Type - The type of DFH (e.g. FME, AFU, or private feature).
97   * EOL - Set if the DFH is the end of the Device Feature List (DFL).
100     If EOL is set, Next is the size of MMIO of the last feature in the list.
101   * REV - The revision of the feature associated with this header.
102   * ID - The feature ID if Type is private feature.
115 Device Feature Header - Version 1
117 Version 1 (DFHv1) of the Device Feature Header adds the following functionality:
122 * Decouples the DFH location from the register space of the feature itself.
125 The format of Version 1 of the Device Feature Header (DFH) is shown below::
153   * Type - The type of DFH (e.g. FME, AFU, or private feature).
156   * EOL - Set if the DFH is the end of the Device Feature List (DFL).
159     If EOL is set, Next is the size of MMIO of the last feature in the list.
160   * REV - The revision of the feature associated with this header.
161   * ID - The feature ID if Type is private feature.
174     of a 16-bit aligned absolute address of the feature's registers. Otherwise
175     the value is the offset from the start of the DFH of the feature's registers.
179   * Reg Size - Size of feature's register set in bytes.
181   * Group - Id of group if feature is part of a group.
182   * Instance - Id of feature instance within a group.
184 - Offset 0x28 if feature has parameters
308                  | FPGA Container Device |    Device Feature List
321 (FPGA base region), discover feature devices and their private features from the
322 given Device Feature Lists and create platform devices for feature devices
325 feature device drivers.
343 	   bridges and FPGA regions during PR sub feature initialization. Once
354 After feature platform devices creation, matched platform drivers will be loaded
379 Feature Lists, as illustrated below:
482 Application needs to search each regionX folder, if feature device is found,
514 Performance reporting is one private feature implemented in FME. It could
595 many interrupts are supported for this private feature. Drivers also implement
608 new feature dev (FIU) following the same way as existing feature dev drivers
618 framework, as each private feature will be parsed automatically and related
620 Developer only needs to provide a sub feature driver with matched feature id.
621 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
624 Please refer to below link to existing feature id table and guide for new feature
626 https://github.com/OPAE/dfl-feature-id
662 components. New hardware can instantiate a new private feature in the DFL, and
675 Currently the uio_dfl driver only supports the Ether Group sub feature, which
679 new DFL feature via UIO direct access, its feature id should be added to the