Lines Matching full:such
19 passes such pin configuration data to drivers.
25 often have a few such pins to help with pin scarcity on SOCs; and there are
38 of pins configured as "output", which is very useful in such "wire-OR"
43 sometimes level triggered. Such IRQs may be configurable as system
72 optional code supporting such an implementation strategy, described later
114 test if such number from such a structure could reference a GPIO, you
125 of GPIO numbers, and whether new controllers can be added at runtime. Such issues
168 Use the following calls to access such GPIOs::
190 of instructions in such cases (reading or writing a hardware register),
191 and not to need spinlocks. Such optimized calls can make bitbanging
202 To access such GPIOs, a different set of accessors is defined::
210 Accessing such GPIOs requires a context which may sleep, for example
218 **IN ADDITION** calls to setup and configure such GPIOs must be made
262 power management, such as by powering down unused chip sectors and, more
280 Similarly, other aspects of the GPIO or pin may need to be configured, such as
281 pullup/pulldown. Platform software should arrange that any such details are
470 commonly grouped in banks of 16 or 32, with a given SOC having several such
472 from pins not managed as GPIOs. Code relying on such mechanisms will
510 not exposed by the GPIO interfaces, such as addressing, power management,
511 and more. Chips such as codecs will have complex non-GPIO state.
535 cost as little as two or three instructions, never sleeping. When such an
537 code, costing at least a few dozen instructions. For bitbanged I/O, such
543 may well start at zero and go up to a platform-specific limit. Such GPIOs
550 For external GPIO controllers -- such as I2C or SPI expanders, ASICs, multi
564 calls for that GPIO can work. One way to address such dependencies is for
565 such gpio_chip controllers to provide setup() and teardown() callbacks to
683 or other cards in the stack. In such cases, you may need to use the