bindings/pwm/microchip%2Ccorepwm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip IP corePWM controller
11   - Conor Dooley <conor.dooley@microchip.com>
14   corePWM is an 16 channel pulse width modulator FPGA IP
16   https://www.microsemi.com/existing-parts/parts/152118
19   - $ref: pwm.yaml#
24       - const: microchip,corepwm-rtl-v4
32   "#pwm-cells":
37   microchip,sync-update-mask:
39       Depending on how the IP is instantiated, there are two modes of operation.
42       A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
44       FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
48       Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
54   microchip,dac-mode-mask:
56       Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
59       standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
60       core, set at instantiation and by the bitstream programmed to the FPGA, determines
69   - compatible
70   - reg
71   - clocks
76   - |
78       compatible = "microchip,corepwm-rtl-v4";
79       microchip,sync-update-mask = /bits/ 32 <0>;
82       #pwm-cells = <2>;