bindings/pci/rcar-gen4-pci-ep.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Endpoint
11   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14   - $ref: snps,dw-pcie-ep.yaml#
19       - const: renesas,r8a779f0-pcie-ep   # R-Car S4-8
20       - const: renesas,rcar-gen4-pcie-ep  # R-Car Gen4
25   reg-names:
27       - const: dbi
28       - const: dbi2
29       - const: atu
30       - const: dma
31       - const: app
32       - const: phy
33       - const: addr_space
38   interrupt-names:
40       - const: dma
41       - const: sft_ce
42       - const: app
47   clock-names:
49       - const: core
50       - const: ref
52   power-domains:
58   reset-names:
60       - const: pwr
62   max-link-speed:
65   num-lanes:
68   max-functions:
72   - compatible
73   - reg
74   - reg-names
75   - interrupts
76   - interrupt-names
77   - clocks
78   - clock-names
79   - power-domains
80   - resets
81   - reset-names
86   - |
87     #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
88     #include <dt-bindings/interrupt-controller/arm-gic.h>
89     #include <dt-bindings/power/r8a779f0-sysc.h>
92         #address-cells = <2>;
93         #size-cells = <2>;
95         pcie0_ep: pcie-ep@e65d0000 {
96             compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
101             reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
105             interrupt-names = "dma", "sft_ce", "app";
107             clock-names = "core", "ref";
108             power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
110             reset-names = "pwr";
111             max-link-speed = <4>;
112             num-lanes = <2>;
113             max-functions = /bits/ 8 <2>;