Lines Matching +full:magic +full:- +full:packet
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
22 - enum:
23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
25 - const: cdns,gem # Generic
28 - items:
29 - enum:
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
33 - const: cdns,gem # Generic
35 - items:
36 - enum:
37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38 - cdns,sam9x60-macb # Microchip sam9x60 SoC
39 - microchip,mpfs-macb # Microchip PolarFire SoC
40 - const: cdns,macb # Generic
42 - items:
43 - enum:
44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
45 - enum:
46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
47 - const: cdns,macb # Generic
49 - enum:
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
54 - cdns,np4-macb # NP4 SoC devices
55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
58 - cdns,emac # Generic
59 - cdns,gem # Generic
60 - cdns,macb # Generic
65 - description: Basic register set
66 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
77 clock-names:
80 - enum: [ ether_clk, hclk, pclk ]
81 - enum: [ hclk, pclk ]
82 - const: tx_clk
83 - enum: [ rx_clk, tsu_clk ]
84 - const: tsu_clk
86 local-mac-address: true
88 phy-mode: true
90 phy-handle: true
99 controller instance with zynqmp-reset driver.
101 reset-names:
104 fixed-link: true
109 power-domains:
112 cdns,rx-watermark:
116 the receiver will only begin to forward the packet to the external
117 AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
118 rx-watermark corresponds to the number of SRAM buffer locations,
122 '#address-cells':
125 '#size-cells':
135 "^ethernet-phy@[0-9a-f]$":
137 $ref: ethernet-phy.yaml#
140 reset-gpios: true
142 magic-packet:
145 Indicates that the hardware supports waking up via magic packet.
150 - compatible
151 - reg
152 - interrupts
153 - clocks
154 - clock-names
155 - phy-mode
158 - $ref: ethernet-controller.yaml#
160 - if:
165 const: sifive,fu540-c000-gem
174 - |
179 cdns,rx-watermark = <0x44>;
180 phy-mode = "rmii";
181 local-mac-address = [3a 0e 03 04 05 06];
182 clock-names = "pclk", "hclk", "tx_clk";
184 #address-cells = <1>;
185 #size-cells = <0>;
187 ethernet-phy@1 {
189 reset-gpios = <&pioE 6 1>;
193 - |
194 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
195 #include <dt-bindings/power/xlnx-zynqmp-power.h>
196 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
197 #include <dt-bindings/phy/phy.h>
200 #address-cells = <2>;
201 #size-cells = <2>;
203 compatible = "xlnx,zynqmp-gem", "cdns,gem";
204 interrupt-parent = <&gic>;
210 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
211 #address-cells = <1>;
212 #size-cells = <0>;
214 power-domains = <&zynqmp_firmware PD_ETH_1>;
216 reset-names = "gem1_rst";
217 phy-mode = "sgmii";
219 fixed-link {
221 full-duplex;