bindings/mtd/atmel-nand.txt

4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 	"atmel,at91rm9200-nand-controller"
13 	"atmel,at91sam9260-nand-controller"
14 	"atmel,at91sam9261-nand-controller"
15 	"atmel,at91sam9g45-nand-controller"
16 	"atmel,sama5d3-nand-controller"
17 	"microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
20 - #size-cells: should be set to 1.
21 - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
23 - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
34        exposes multiple CS lines (multi-dies chips), your reg property will
39        3rd entry: the memory region size (always 0x800000)
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
43 - cs-gpios: the GPIO(s) used to control the CS line.
44 - det-gpios: the GPIO used to detect if a Smartmedia Card is present.
45 - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
51 * ECC engine (PMECC) bindings:
54 - compatible: should be one of the following
55 	"atmel,at91sam9g45-pmecc"
56 	"atmel,sama5d4-pmecc"
57 	"atmel,sama5d2-pmecc"
58 	"microchip,sam9x60-pmecc"
59 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
68 - compatible: should be "atmel,sama5d3-nfc-io", "syscon".
69 - reg: should contain the I/O range used to interact with the NFC logic.
73 	nfc_io: nfc-io@70000000 {
74 		compatible = "atmel,sama5d3-nfc-io", "syscon";
78 	pmecc: ecc-engine@ffffc070 {
79 		compatible = "atmel,at91sam9g45-pmecc";
85 		compatible = "atmel,sama5d3-ebi";
86 		#address-cells = <2>;
87 		#size-cells = <1>;
97                 nand_controller: nand-controller {
98 			compatible = "atmel,sama5d3-nand-controller";
99 			atmel,nfc-sram = <&nfc_sram>;
100 			atmel,nfc-io = <&nfc_io>;
101 			ecc-engine = <&pmecc>;
102 			#address-cells = <2>;
103 			#size-cells = <1>;
118 -----------------------------------------------------------------------
123 - compatible: The possible values are:
124 	"atmel,at91rm9200-nand"
125 	"atmel,sama5d2-nand"
126 	"atmel,sama5d4-nand"
127 - reg : should specify localbus address and size used for the chip,
128 	and hardware ECC controller if available.
129 	If the hardware ECC is PMECC, it should contain address and size for
131 	The PMECC lookup table address and size in ROM is optional. If not
133 - atmel,nand-addr-offset : offset for the address latch.
134 - atmel,nand-cmd-offset : offset for the command latch.
135 - #address-cells, #size-cells : Must be present if the device has sub-nodes
138 - gpios : specifies the gpio pins to control the NAND device. detect is an
142 - atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
143 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
146 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
148 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
150   is "atmel,sama5d2-nand", 32 is also valid.
151 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
153 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
154   for different sector size. First one is for sector size 512, the next is for
155   sector size 1024. If not specified, driver will build the table in runtime.
156 - nand-bus-width : 8 or 16 bus width if not present 8
157 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
159 Nand Flash Controller(NFC) is an optional sub-node
161 - compatible : "atmel,sama5d3-nfc".
162 - reg : should specify the address and size used for NFC command registers,
163         NFC registers and NFC SRAM. NFC SRAM address and size can be absent
165 - clocks: phandle to the peripheral clock
167 - atmel,write-by-sram: boolean to enable NFC write by SRAM.
171 	compatible = "atmel,at91rm9200-nand";
172 	#address-cells = <1>;
173 	#size-cells = <1>;
177 	atmel,nand-addr-offset = <21>;	/* ale */
178 	atmel,nand-cmd-offset = <22>;	/* cle */
179 	nand-on-flash-bbt;
180 	nand-ecc-mode = "soft";
192 	compatible = "atmel,at91rm9200-nand";
193 	#address-cells = <1>;
194 	#size-cells = <1>;
195 	reg = < 0x40000000 0x10000000	/* bus addr & size */
196 		0xffffe000 0x00000600	/* PMECC addr & size */
197 		0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
198 		0x00100000 0x00100000	/* ROM addr & size */
200 	atmel,nand-addr-offset = <21>;	/* ale */
201 	atmel,nand-cmd-offset = <22>;	/* cle */
202 	nand-on-flash-bbt;
203 	nand-ecc-mode = "hw";
204 	atmel,has-pmecc;	/* enable PMECC */
205 	atmel,pmecc-cap = <2>;
206 	atmel,pmecc-sector-size = <512>;
207 	atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
219 	compatible = "atmel,at91rm9200-nand";
220 	#address-cells = <1>;
221 	#size-cells = <1>;
225 		compatible = "atmel,sama5d3-nfc";
226 		#address-cells = <1>;
227 		#size-cells = <1>;