bindings/memory-controllers/xlnx%2Cversal-ddrmc-edac.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11   - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
20     const: xlnx,versal-ddrmc
22   reg:
24       - description: DDR Memory Controller registers
25       - description: NOC registers corresponding to DDR Memory Controller
27   reg-names:
29       - const: base
30       - const: noc
36   - compatible
37   - reg
38   - reg-names
39   - interrupts
44   - |
45     #include <dt-bindings/interrupt-controller/arm-gic.h>
48       #address-cells = <2>;
49       #size-cells = <2>;
50       memory-controller@f6150000 {
51         compatible = "xlnx,versal-ddrmc";
52         reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
53         reg-names = "base", "noc";
54         interrupt-parent = <&gic>;